Nagi Aboulenein

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Parity protected memory blocks merged with error correction code (E...
- Patent number 11,934,263
- Issue date Mar 19, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, and system for run-time checking of memory tags...
- Patent number 11,586,537
- Issue date Feb 21, 2023
- Ampere Computing LLC
- Benjamin Crawford Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coarse tag replacement
- Patent number 10,621,094
- Issue date Apr 14, 2020
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interference testing
- Patent number 10,516,439
- Issue date Dec 24, 2019
- Intel Corporation
- Alexey Kostinsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated error checking and correction (ECC) in byte mode memory...
- Patent number 10,482,947
- Issue date Nov 19, 2019
- Intel Corporation
- Christopher E. Cox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared command address (C/A) bus for multiple memory channels
- Patent number 9,940,984
- Issue date Apr 10, 2018
- Intel Corporation
- MD Altaf Hossain
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic power measurement and estimation to improve memory subsyste...
- Patent number 9,851,771
- Issue date Dec 26, 2017
- Intel Corporation
- Lawrence A Cooper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interference testing
- Patent number 9,722,663
- Issue date Aug 1, 2017
- Intel Corporation
- Alexey Kostinsky
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method to dynamically expand associativity of a cache...
- Patent number 9,514,047
- Issue date Dec 6, 2016
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configuration of data strobes
- Patent number 9,268,724
- Issue date Feb 23, 2016
- Intel Corporation
- Md Altaf Hossain
- G11 - INFORMATION STORAGE
Information Patent Grant
Prefetch optimization in shared resource multi-core systems
- Patent number 8,924,651
- Issue date Dec 30, 2014
- Intel Corporation
- Perry P. Tang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Configuration of data strobes
- Patent number 8,683,096
- Issue date Mar 25, 2014
- Intel Corporation
- Md Altaf Hossain
- G11 - INFORMATION STORAGE
Information Patent Grant
Prefetch optimization in shared resource multi-core systems
- Patent number 8,443,151
- Issue date May 14, 2013
- Intel Corporation
- Puqi P. Tang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for out of order memory scheduling
- Patent number 7,127,574
- Issue date Oct 24, 2006
- Intel Corporatioon
- Hemant G. Rotithor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetching data for peripheral component interconnect devices
- Patent number 6,792,496
- Issue date Sep 14, 2004
- Intel Corporation
- Nagi Aboulenein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for memory access scheduling to reduce memory...
- Patent number 6,785,793
- Issue date Aug 31, 2004
- Intel Corporation
- Nagi Aboulenein
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...
- Publication number 20240220356
- Publication date Jul 4, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS IN A PROCESSOR-BASED...
- Publication number 20240004577
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPONENT DIE VALIDATION BUILT-IN SELF-TEST (VBIST) ENGINE
- Publication number 20240003974
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Sandeep BRAHMADATHAN
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED ERROR CORRECTION CODE (ECC) AND PARITY PROTECTION IN MEM...
- Publication number 20230315571
- Publication date Oct 5, 2023
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...
- Publication number 20230315565
- Publication date Oct 5, 2023
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS-RANGE MEMORY MIRRORING IN A COMPUTER SYSTEM, AND RELATED ME...
- Publication number 20230176749
- Publication date Jun 8, 2023
- Ampere Computing LLC
- Sebastien Hily
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR RUN-TIME CHECKING OF MEMORY TAGS...
- Publication number 20220043748
- Publication date Feb 10, 2022
- Ampere Computing LLC
- Benjamin Crawford Chaffin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS RANGE BASED IN-BAND MEMORY ERROR-CORRECTING CODE PROTECTION...
- Publication number 20190332469
- Publication date Oct 31, 2019
- Intel Corporation
- Amir A. RADJAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG CACHE ADAPTIVE POWER GATING
- Publication number 20190102314
- Publication date Apr 4, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COARSE TAG REPLACEMENT
- Publication number 20190004952
- Publication date Jan 3, 2019
- Intel Corporation
- Zhe Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED ERROR CHECKING AND CORRECTION (ECC) IN BYTE MODE MEMORY...
- Publication number 20180254079
- Publication date Sep 6, 2018
- Intel Corporation
- Christopher E. COX
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED COMMAND ADDRESS (C/A) BUS FOR MULTIPLE MEMORY CHANNELS
- Publication number 20180090185
- Publication date Mar 29, 2018
- Intel Corporation
- MD Altaf HOSSAIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFERENCE TESTING
- Publication number 20170359099
- Publication date Dec 14, 2017
- Intel Corporation
- Alexey Kostinsky
- G01 - MEASURING TESTING
Information Patent Application
Apparatus and Method to Dynamically Expand Associativity of A Cache...
- Publication number 20160179666
- Publication date Jun 23, 2016
- Intel Corporation
- Daniel Greenspan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC POWER MEASUREMENT AND ESTIMATION TO IMPROVE MEMORY SUBSYSTE...
- Publication number 20150185797
- Publication date Jul 2, 2015
- Lawrence A. Cooper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION OF DATA STROBES
- Publication number 20140317343
- Publication date Oct 23, 2014
- Md Altaf Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH OPTIMIZATION IN SHARED RESOURCE MULTI-CORE SYSTEMS
- Publication number 20140136795
- Publication date May 15, 2014
- PERRY P. TANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION OF DATA STROBES
- Publication number 20140003169
- Publication date Jan 2, 2014
- Md Altaf Hossain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH OPTIMIZATION IN SHARED RESOURCE MULTI-CORE SYSTEMS
- Publication number 20110113199
- Publication date May 12, 2011
- Puqi P. Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mechanism for write optimization to a memory device
- Publication number 20080162799
- Publication date Jul 3, 2008
- Bryan Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for out of order memory scheduling
- Publication number 20050091460
- Publication date Apr 28, 2005
- Hemant G. Rotithor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for memory access scheduling to reduce memory...
- Publication number 20030061459
- Publication date Mar 27, 2003
- Nagi Aboulenein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Prefetching data for peripheral component interconnect devices
- Publication number 20030028694
- Publication date Feb 6, 2003
- Nagi Aboulenein
- G06 - COMPUTING CALCULATING COUNTING

Nagi Aboulenein

Person

Patents Grantslast 30 patents

Parity protected memory blocks merged with error correction code (E...

Method, apparatus, and system for run-time checking of memory tags...

Coarse tag replacement

Interference testing

Integrated error checking and correction (ECC) in byte mode memory...

Shared command address (C/A) bus for multiple memory channels

Dynamic power measurement and estimation to improve memory subsyste...

Interference testing

Apparatus and method to dynamically expand associativity of a cache...

Configuration of data strobes

Prefetch optimization in shared resource multi-core systems

Configuration of data strobes

Prefetch optimization in shared resource multi-core systems

Method and apparatus for out of order memory scheduling

Prefetching data for peripheral component interconnect devices

Method and apparatus for memory access scheduling to reduce memory...

Patents Applicationslast 30 patents

PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...

EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS IN A PROCESSOR-BASED...

COMPONENT DIE VALIDATION BUILT-IN SELF-TEST (VBIST) ENGINE

INTEGRATED ERROR CORRECTION CODE (ECC) AND PARITY PROTECTION IN MEM...

PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...

ADDRESS-RANGE MEMORY MIRRORING IN A COMPUTER SYSTEM, AND RELATED ME...

METHOD, APPARATUS, AND SYSTEM FOR RUN-TIME CHECKING OF MEMORY TAGS...

ADDRESS RANGE BASED IN-BAND MEMORY ERROR-CORRECTING CODE PROTECTION...

TAG CACHE ADAPTIVE POWER GATING

COARSE TAG REPLACEMENT

INTEGRATED ERROR CHECKING AND CORRECTION (ECC) IN BYTE MODE MEMORY...

SHARED COMMAND ADDRESS (C/A) BUS FOR MULTIPLE MEMORY CHANNELS

INTERFERENCE TESTING

Apparatus and Method to Dynamically Expand Associativity of A Cache...

DYNAMIC POWER MEASUREMENT AND ESTIMATION TO IMPROVE MEMORY SUBSYSTE...

CONFIGURATION OF DATA STROBES

PREFETCH OPTIMIZATION IN SHARED RESOURCE MULTI-CORE SYSTEMS

CONFIGURATION OF DATA STROBES

PREFETCH OPTIMIZATION IN SHARED RESOURCE MULTI-CORE SYSTEMS

Mechanism for write optimization to a memory device

Method and apparatus for out of order memory scheduling

Method and apparatus for memory access scheduling to reduce memory...

Prefetching data for peripheral component interconnect devices