Naishad Narendra Parikh

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Bangalore, IN

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Patents Grantslast 30 patents

Information Patent Grant
Memory hold margin characterization and correction circuit
- Patent number 10,622,044
- Issue date Apr 14, 2020
- QUALCOMM Incorporated
- Bipin Duggal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan chain in an integrated circuit
- Patent number 9,097,764
- Issue date Aug 4, 2015
- Texas Instruments Incorporated
- Naishad Narendra Parikh
- G01 - MEASURING TESTING
Information Patent Grant
Programmable scannable storage circuit
- Patent number 8,749,286
- Issue date Jun 10, 2014
- Texas Instruments Incorporated
- Pranjal Tiwari
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MEMORY HOLD MARGIN CHARACTERIZATION AND CORRECTION CIRCUIT
- Publication number 20190096460
- Publication date Mar 28, 2019
- QUALCOMM Incorporated
- Bipin DUGGAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN CHAIN IN AN INTEGRATED CIRCUIT
- Publication number 20140208176
- Publication date Jul 24, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Naishad Narendra Parikh
- G01 - MEASURING TESTING
Information Patent Application
Programmable Scannable Storage Circuit
- Publication number 20130057329
- Publication date Mar 7, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Pranjal Tiwari
- G01 - MEASURING TESTING