Nam Sung Kim

Person

Middleton, WI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Computer architecture having selectable parallel and serial communi...
- Patent number 12,140,992
- Issue date Nov 12, 2024
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer architecture having selectable, parallel and serial commun...
- Patent number 11,755,060
- Issue date Sep 12, 2023
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer architecture having selectable, parallel and serial commun...
- Patent number 10,108,220
- Issue date Oct 23, 2018
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared row buffer system for asymmetric memory
- Patent number 9,959,205
- Issue date May 1, 2018
- Wisconsin Alumni Research Foundation
- Hao Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for power reduction during lane divergence
- Patent number 9,690,350
- Issue date Jun 27, 2017
- Advances Micro Devices, Inc.
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for heterogeneous computer
- Patent number 9,665,290
- Issue date May 30, 2017
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplication circuit providing dynamic truncation
- Patent number 9,639,328
- Issue date May 2, 2017
- Wisconsin Alumni Research Foundation
- Srinivasan Narayanamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory fault patching using pre-existing memory structures
- Patent number 9,626,297
- Issue date Apr 18, 2017
- Wisconsin Alumni Research Foundation
- David John Palframan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource and core scaling for improving performance of power-constr...
- Patent number 9,606,842
- Issue date Mar 28, 2017
- National Science Foundation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for adjusting bandwidth
- Patent number 9,588,570
- Issue date Mar 7, 2017
- Samsung Electronics Co., Ltd.
- Ho-Young Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage regulator control for improved computing power efficiency
- Patent number 9,547,355
- Issue date Jan 17, 2017
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High efficiency computer floating point multiplier unit
- Patent number 9,519,459
- Issue date Dec 13, 2016
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy-efficient multicore processor architecture for parallel proc...
- Patent number 9,519,330
- Issue date Dec 13, 2016
- Wisconsin Alumni Research Foundation
- Nam-Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for heterogeneous computer
- Patent number 9,501,227
- Issue date Nov 22, 2016
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal processing circuit with multiple power modes
- Patent number 9,497,381
- Issue date Nov 15, 2016
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic error handling for on-chip memory structures
- Patent number 9,323,614
- Issue date Apr 26, 2016
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiplier circuit with dynamic energy consumption adjustment
- Patent number 9,323,498
- Issue date Apr 26, 2016
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for soft error mitigation in computers
- Patent number 9,235,461
- Issue date Jan 12, 2016
- Wisconsin Alumni Research Foundation
- David John Palframan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-link compression for graphic processor unit
- Patent number 9,189,394
- Issue date Nov 17, 2015
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Leakage power management using programmable power gating transistor...
- Patent number 8,736,314
- Issue date May 27, 2014
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Energy efficient processor having heterogeneous cache
- Patent number 8,687,453
- Issue date Apr 1, 2014
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Method and apparatus for optimizing clock speed and power dissipati...
- Patent number 8,281,164
- Issue date Oct 2, 2012
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
Computer Architecture Having Selectable Parallel and Serial Communi...
- Publication number 20240402752
- Publication date Dec 5, 2024
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computer Architecture Having Selectable Parallel and Serial Communi...
- Publication number 20240004419
- Publication date Jan 4, 2024
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Computer Architecture Having Selectable, Parallel and Serial Commun...
- Publication number 20190041897
- Publication date Feb 7, 2019
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Controller for Heterogeneous Computer
- Publication number 20170060441
- Publication date Mar 2, 2017
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shared Row Buffer System For Asymmetric Memory
- Publication number 20160335181
- Publication date Nov 17, 2016
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Signal Processing Circuit with Multiple Power Modes
- Publication number 20160205321
- Publication date Jul 14, 2016
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory Fault Patching Using Pre-Existing Memory Structures
- Publication number 20160103729
- Publication date Apr 14, 2016
- Wisconsin Alumni Research Foundation
- David John Palframan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Controller for Heterogeneous Computer
- Publication number 20160054932
- Publication date Feb 25, 2016
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage Regulator Control for Improved Computing Power Efficiency
- Publication number 20160048188
- Publication date Feb 18, 2016
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiplication Circuit Providing Dynamic Truncation
- Publication number 20160041813
- Publication date Feb 11, 2016
- Wisconsin Alumni Research Foundation
- Srinivasan Narayanamoorthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High Efficiency Computer Floating Point Multiplier Unit
- Publication number 20150370537
- Publication date Dec 24, 2015
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER ARCHITECTURE HAVING SELECTABLE, PARALLEL AND SERIAL COMMUN...
- Publication number 20150317277
- Publication date Nov 5, 2015
- Wisconsin Alumni Research Foundation
- Hao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Soft Error Mitigation in Computers
- Publication number 20150234693
- Publication date Aug 20, 2015
- Wisconsin Alumni Research Foundation
- David John Palframan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Error Handling For On-Chip Memory Structures
- Publication number 20150128007
- Publication date May 7, 2015
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENERGY-EFFICIENT MULTICORE PROCESSOR ARCHITECTURE FOR PARALLEL PROC...
- Publication number 20150113304
- Publication date Apr 23, 2015
- Wisconsin Alumni Research Foundation
- Nam-Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resource And Core Scaling For Improving Performance Of Power-Constr...
- Publication number 20140337853
- Publication date Nov 13, 2014
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ADJUSTING BANDWIDTH
- Publication number 20140325248
- Publication date Oct 30, 2014
- Wisconsin Alumni Research Foundation
- Ho-Young KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiplier Circuit with Dynamic Energy Consumption Adjustment
- Publication number 20140280430
- Publication date Sep 18, 2014
- Wisconsin Alumni Research Foundation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR POWER REDUCTION DURING LANE DIVERGENCE
- Publication number 20140068304
- Publication date Mar 6, 2014
- Advanced Micro Devices, Inc.
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Link Compression for Graphic Processor Unit
- Publication number 20140047199
- Publication date Feb 13, 2014
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Energy Efficient Processor Having Heterogeneous Cache
- Publication number 20130094318
- Publication date Apr 18, 2013
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Optimizing Clock Speed and Power Dissipati...
- Publication number 20120042176
- Publication date Feb 16, 2012
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING

Nam Sung Kim

Person

Patents Grantslast 30 patents

Computer architecture having selectable parallel and serial communi...

Computer architecture having selectable, parallel and serial commun...

Computer architecture having selectable, parallel and serial commun...

Shared row buffer system for asymmetric memory

Method and apparatus for power reduction during lane divergence

Memory controller for heterogeneous computer

Multiplication circuit providing dynamic truncation

Memory fault patching using pre-existing memory structures

Resource and core scaling for improving performance of power-constr...

Apparatus and method for adjusting bandwidth

Voltage regulator control for improved computing power efficiency

High efficiency computer floating point multiplier unit

Energy-efficient multicore processor architecture for parallel proc...

Memory controller for heterogeneous computer

Signal processing circuit with multiple power modes

Dynamic error handling for on-chip memory structures

Multiplier circuit with dynamic energy consumption adjustment

Method and apparatus for soft error mitigation in computers

Memory-link compression for graphic processor unit

Leakage power management using programmable power gating transistor...

Energy efficient processor having heterogeneous cache

Method and apparatus for optimizing clock speed and power dissipati...

Patents Applicationslast 30 patents

Computer Architecture Having Selectable Parallel and Serial Communi...

Computer Architecture Having Selectable Parallel and Serial Communi...

Computer Architecture Having Selectable, Parallel and Serial Commun...

Memory Controller for Heterogeneous Computer

Shared Row Buffer System For Asymmetric Memory

Signal Processing Circuit with Multiple Power Modes

Memory Fault Patching Using Pre-Existing Memory Structures

Memory Controller for Heterogeneous Computer

Voltage Regulator Control for Improved Computing Power Efficiency

Multiplication Circuit Providing Dynamic Truncation

High Efficiency Computer Floating Point Multiplier Unit

COMPUTER ARCHITECTURE HAVING SELECTABLE, PARALLEL AND SERIAL COMMUN...

Method and Apparatus for Soft Error Mitigation in Computers

Dynamic Error Handling For On-Chip Memory Structures

ENERGY-EFFICIENT MULTICORE PROCESSOR ARCHITECTURE FOR PARALLEL PROC...

Resource And Core Scaling For Improving Performance Of Power-Constr...

APPARATUS AND METHOD FOR ADJUSTING BANDWIDTH

Multiplier Circuit with Dynamic Energy Consumption Adjustment

METHOD AND APPARATUS FOR POWER REDUCTION DURING LANE DIVERGENCE

Memory-Link Compression for Graphic Processor Unit

Energy Efficient Processor Having Heterogeneous Cache

Method and Apparatus for Optimizing Clock Speed and Power Dissipati...