Naokazu Miyawaki

Person

Yokohama, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus for controlling circuit response during power-up
- Patent number 5,995,436
- Issue date Nov 30, 1999
- Siemens Aktiengesellschaft
- Martin Brox
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus for controlling circuit response during power-up
- Patent number 5,881,013
- Issue date Mar 9, 1999
- Siemens Aktiengesellschaft
- Martin Brox
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit including ring oscillator of low c...
- Patent number 5,544,120
- Issue date Aug 6, 1996
- Kabushiki Kaisha Toshiba
- Masaaki Kuwagata
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 5,381,372
- Issue date Jan 10, 1995
- Kabushiki Kaisha Toshiba
- Eiji Kozuka
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 5,337,286
- Issue date Aug 9, 1994
- Kabushiki Kaisha Toshiba
- Osamu Ohto
- G11 - INFORMATION STORAGE
Information Patent Grant
Control circuit for controlling an operation mode in a pseudo-stati...
- Patent number 5,301,164
- Issue date Apr 5, 1994
- Kabushiki Kaisha Toshiba
- Naokazu Miyawaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 5,278,798
- Issue date Jan 11, 1994
- Kabushiki Kaisha Toshiba
- Naokazu Miyawaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Impedance control circuit for a semiconductor substrate
- Patent number 5,270,583
- Issue date Dec 14, 1993
- Kabushiki Kaisha Toshiba
- Naokazu Miyawaki
- G05 - CONTROLLING REGULATING
Information Patent Grant
Substrate bias voltage generator circuit
- Patent number 5,243,228
- Issue date Sep 7, 1993
- Kabushiki Kaisha Toshiba
- Keiji Maruyama
- G05 - CONTROLLING REGULATING
Information Patent Grant
Chip enable input circuit in semiconductor memory device
- Patent number 4,970,694
- Issue date Nov 13, 1990
- Kabushiki Kaisha Toshiba
- Hiroaki Tanaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer circuit for minimizing noise in an integrated circuit
- Patent number 4,754,170
- Issue date Jun 28, 1988
- Kabushiki Kaisha Toshiba
- Haruki Toda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory clock pulse generating circuit with reduced peak current req...
- Patent number 4,644,184
- Issue date Feb 17, 1987
- Tokyo Shibaura Denki Kabushiki Kaisha
- Naokazu Miyawaki
- G11 - INFORMATION STORAGE

Naokazu Miyawaki

Person

Patents Grantslast 30 patents

Apparatus for controlling circuit response during power-up

Apparatus for controlling circuit response during power-up

Semiconductor integrated circuit including ring oscillator of low c...

Semiconductor memory device

Semiconductor memory device

Control circuit for controlling an operation mode in a pseudo-stati...

Semiconductor memory device

Impedance control circuit for a semiconductor substrate

Substrate bias voltage generator circuit

Chip enable input circuit in semiconductor memory device

Buffer circuit for minimizing noise in an integrated circuit

Memory clock pulse generating circuit with reduced peak current req...