Narasimha R. Lanka

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Approximate data bus inversion technique for latency sensitive appl...
- Patent number 12,117,960
- Issue date Oct 15, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link layer-PHY interface adapter
- Patent number 11,971,841
- Issue date Apr 30, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technology to provide accurate training and per-bit deskew capabili...
- Patent number 11,954,360
- Issue date Apr 9, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 11,599,497
- Issue date Mar 7, 2023
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 10,789,201
- Issue date Sep 29, 2020
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, system for centering in a high performance inter...
- Patent number 10,560,081
- Issue date Feb 11, 2020
- Intel Corporation
- Mahesh Wagh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus, system for centering in a high performance inter...
- Patent number 9,692,402
- Issue date Jun 27, 2017
- Intel Corporation
- Mahesh Wagh
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...
- Publication number 20240311330
- Publication date Sep 19, 2024
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING
- Publication number 20230258716
- Publication date Aug 17, 2023
- Intel Corporation
- Swadesh Choudhary
- G01 - MEASURING TESTING
Information Patent Application
MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...
- Publication number 20230230923
- Publication date Jul 20, 2023
- Intel Corporation
- Gerald Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE-TO-DIE INTERCONNECT
- Publication number 20220342840
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE ADAPTER
- Publication number 20220342841
- Publication date Oct 27, 2022
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT
- Publication number 20220334932
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT
- Publication number 20220334995
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...
- Publication number 20220327276
- Publication date Oct 13, 2022
- Intel Corporation
- Lakshmipriya Seshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
- Publication number 20220327084
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
- Publication number 20220327083
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT
- Publication number 20220318111
- Publication date Oct 6, 2022
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT
- Publication number 20220271912
- Publication date Aug 25, 2022
- Gerald Pasdast
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS
- Publication number 20220262756
- Publication date Aug 18, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS
- Publication number 20220261308
- Publication date Aug 18, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT
- Publication number 20220237138
- Publication date Jul 28, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS
- Publication number 20220222198
- Publication date Jul 14, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Control Apparatus, Device, Method and Computer Program for Determin...
- Publication number 20220011795
- Publication date Jan 13, 2022
- Intel Corporation
- Michael RIFANI
- G01 - MEASURING TESTING
Information Patent Application
PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES
- Publication number 20210344354
- Publication date Nov 4, 2021
- Intel Corporation
- Narasimha Lanka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOGIC DIE IN A MULTI-CHIP PACKAGE HAVING A CONFIGURABLE PHYSICAL IN...
- Publication number 20210225827
- Publication date Jul 22, 2021
- Intel Corporation
- Narasimha LANKA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCTION OF LATENCY IMPACT OF ON-DIE ERROR CHECKING AND CORRECTION...
- Publication number 20210224155
- Publication date Jul 22, 2021
- Intel Corporation
- Kuljit S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPL...
- Publication number 20210004347
- Publication date Jan 7, 2021
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK LAYER-PHY INTERFACE ADAPTER
- Publication number 20200394150
- Publication date Dec 17, 2020
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20200394151
- Publication date Dec 17, 2020
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGY TO PROVIDE ACCURATE TRAINING AND PER-BIT DESKEW CAPABILI...
- Publication number 20200393997
- Publication date Dec 17, 2020
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED MEMORY DEVICE WITH END TO END DATA BUS INVERSION
- Publication number 20200251159
- Publication date Aug 6, 2020
- Intel Corporation
- Narasimha Lanka
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20180253398
- Publication date Sep 6, 2018
- Intel Corporation
- Zuoguo Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH PERFORMANCE INTER...
- Publication number 20170294906
- Publication date Oct 12, 2017
- Intel Corporation
- Mahesh Wagh
- G01 - MEASURING TESTING
Information Patent Application
METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH PERFORMANCE INTER...
- Publication number 20160191034
- Publication date Jun 30, 2016
- Intel Corporation
- Mahesh Wagh
- G01 - MEASURING TESTING

Narasimha R. Lanka

Person

Patents Grantslast 30 patents

Approximate data bus inversion technique for latency sensitive appl...

Link layer-PHY interface adapter

Technology to provide accurate training and per-bit deskew capabili...

High performance interconnect

High performance interconnect

Method, apparatus, system for centering in a high performance inter...

Method, apparatus, system for centering in a high performance inter...

Patents Applicationslast 30 patents

ON-ON-PACKAGE DIE-TO-DIE (D2D) INTERCONNECT FOR MEMORY USING UNIVER...

TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING

MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...

DIE-TO-DIE INTERCONNECT

DIE-TO-DIE ADAPTER

RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT

PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT

LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...

DIE-TO-DIE INTERCONNECT PROTOCOL LAYER

STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS

COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT

CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT

CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS

VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS

LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT

SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS

Control Apparatus, Device, Method and Computer Program for Determin...

PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES

LOGIC DIE IN A MULTI-CHIP PACKAGE HAVING A CONFIGURABLE PHYSICAL IN...

REDUCTION OF LATENCY IMPACT OF ON-DIE ERROR CHECKING AND CORRECTION...

APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPL...

LINK LAYER-PHY INTERFACE ADAPTER

HIGH PERFORMANCE INTERCONNECT

TECHNOLOGY TO PROVIDE ACCURATE TRAINING AND PER-BIT DESKEW CAPABILI...

STACKED MEMORY DEVICE WITH END TO END DATA BUS INVERSION

HIGH PERFORMANCE INTERCONNECT

METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH PERFORMANCE INTER...

METHOD, APPARATUS, SYSTEM FOR CENTERING IN A HIGH PERFORMANCE INTER...