Narasimhan Vasudevan

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San Diego, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Clock alignment scheme for data macros of DDR PHY
- Patent number 10,014,866
- Issue date Jul 3, 2018
- Invecas, Inc.
- Narasimhan Vasudevan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock alignment scheme for data macros of DDR PHY
- Patent number 9,954,538
- Issue date Apr 24, 2018
- Invecas, Inc.
- Narasimhan Vasudevan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Receiver architecture for memory reads
- Patent number 9,213,487
- Issue date Dec 15, 2015
- QUALCOMM Incorporated
- Narasimhan Vasudevan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Clock Alignment Scheme for Data Macros of DDR PHY
- Publication number 20180006656
- Publication date Jan 4, 2018
- Invecas, Inc.
- Narasimhan Vasudevan
- G11 - INFORMATION STORAGE
Information Patent Application
Clock Alignment Scheme for Data Macros of DDR PHY
- Publication number 20170373696
- Publication date Dec 28, 2017
- Invecas, Inc.
- Narasimhan Vasudevan
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR REDUCING CROSS-SUPPLY CURRENT
- Publication number 20150108842
- Publication date Apr 23, 2015
- QUALCOMM Incorporated
- Nan Chen
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
DELAY ARCHITECTURE FOR REDUCING DOWNTIME DURING FREQUENCY SWITCHING
- Publication number 20150109034
- Publication date Apr 23, 2015
- QUALCOMM Incorporated
- Narasimhan Vasudevan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RECEIVER ARCHITECTURE FOR MEMORY READS
- Publication number 20150106538
- Publication date Apr 16, 2015
- QUALCOMM Incorporated
- Narasimhan Vasudevan
- G06 - COMPUTING CALCULATING COUNTING