Narendra K. Rane

Follow

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient cache management in a tiled architecture
- Patent number 9,239,795
- Issue date Jan 19, 2016
- NVIDIA Corporation
- Mukesh Chand Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure for window comparator circuit for clock data recovery fro...
- Patent number 8,477,896
- Issue date Jul 2, 2013
- International Business Machines Corporation
- Santoshkumar Jinagar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Automated isolation of logic and macro blocks in chip design testing
- Patent number 8,132,133
- Issue date Mar 6, 2012
- International Business Machines Corporation
- Animesh Khare
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EFFICIENT CACHE MANAGEMENT IN A TILED ARCHITECTURE
- Publication number 20150193903
- Publication date Jul 9, 2015
- NVIDIA Corporation
- Mukesh Chand AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT CACHE MANAGEMENT IN A TILED ARCHITECTURE
- Publication number 20150193907
- Publication date Jul 9, 2015
- NVIDIA Corporation
- Mukesh Chand AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR GAMMA CORRECTION I...
- Publication number 20150103252
- Publication date Apr 16, 2015
- NVIDIA Corporation
- Narendra Keshav Rane
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
AT-SPEED SCAN ENABLE SWITCHING CIRCUIT
- Publication number 20120176144
- Publication date Jul 12, 2012
- International Business Machines Corporation
- Vikram Iyengar
- G01 - MEASURING TESTING
Information Patent Application
DESIGN STRUCTURE FOR WINDOW COMPARATOR CIRCUIT FOR CLOCK DATA RECOV...
- Publication number 20120170698
- Publication date Jul 5, 2012
- International Business Machines Corporation
- Santoshkumar Jinagar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
AUTOMATED ISOLATION OF LOGIC AND MACRO BLOCKS IN CHIP DESIGN TESTING
- Publication number 20100050137
- Publication date Feb 25, 2010
- Animesh Khare
- G06 - COMPUTING CALCULATING COUNTING