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Nasima Parveen
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San Jose, CA, US
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last 30 patents
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Patent Grant
Dual mode AES implementation to support single and multiple AES ope...
Patent number
7,769,166
Issue date
Aug 3, 2010
LSI Corporation
Nasima Parveen
G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information
Patent Grant
Low jitter and/or fast lock-in clock recovery circuit
Patent number
7,545,900
Issue date
Jun 9, 2009
LSI Corporation
Ho-Ming Leung
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Grant
Quotient digit selection logic for floating point division/square root
Patent number
5,954,789
Issue date
Sep 21, 1999
Sun Microsystems, Inc.
Robert K. Yu
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
PROACTIVE DI/DT VOLTAGE DROOP MITIGATION
Publication number
20190384603
Publication date
Dec 19, 2019
Jason Seung-Min Kim
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Dual mode AES implementation to support single and multiple AES ope...
Publication number
20080069339
Publication date
Mar 20, 2008
LSI Logic Corporation
Nasima Parveen
H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information
Patent Application
Low jitter and/or fast lock-in clock recovery circuit
Publication number
20070110206
Publication date
May 17, 2007
LSI Logic Corporation
Ho-Ming Leung
H04 - ELECTRIC COMMUNICATION TECHNIQUE