Natarajan Rohit

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Bandwidth-aware fabric traffic shaping
- Patent number 12,039,169
- Issue date Jul 16, 2024
- Apple Inc.
- Anjana Subramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Allocation of a buffer located in system memory into a cache memory
- Patent number 11,893,251
- Issue date Feb 6, 2024
- Apple Inc.
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pixel array and touch array crosstalk mitigation systems and methods
- Patent number 11,893,185
- Issue date Feb 6, 2024
- Apple Inc.
- Salman Latif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Guaranteed real-time cache carveout for displayed image processing...
- Patent number 11,875,427
- Issue date Jan 16, 2024
- Apple Inc.
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communication channels with both shared and independent resources
- Patent number 11,824,795
- Issue date Nov 21, 2023
- Rohit K. Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configurable interface circuit
- Patent number 11,755,489
- Issue date Sep 12, 2023
- Apple Inc.
- Rohit K. Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic allocation of cache memory as RAM
- Patent number 11,704,245
- Issue date Jul 18, 2023
- Apple Inc.
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application aware SoC memory cache partitioning
- Patent number 11,232,033
- Issue date Jan 25, 2022
- Apple Inc.
- Wolfgang H. Klingauf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-overhead debug architecture using a speculative, concurrent and...
- Patent number 9,547,038
- Issue date Jan 17, 2017
- Samsung Electronics Co., Ltd.
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to merge and align data from distributed memor...
- Patent number 8,370,558
- Issue date Feb 5, 2013
- Intel Corporation
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to merge and align data from distributed memor...
- Patent number 7,480,781
- Issue date Jan 20, 2009
- Intel Corporation
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller with command queue look-ahead
- Patent number 7,418,540
- Issue date Aug 26, 2008
- Intel Corporation
- Natarajan Rohit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus utilizing non-uniformly distributed DRAM confi...
- Patent number 7,213,099
- Issue date May 1, 2007
- Intel Corporation
- Chen-Chi Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for padding and stripping data in response to rea...
- Patent number 7,210,008
- Issue date Apr 24, 2007
- Intel Corporation
- Prashant R. Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packet assembly
- Patent number 7,185,153
- Issue date Feb 27, 2007
- Intel Corporation
- Prashant R. Chandra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
Dynamic Allocation of Cache Memory as RAM
- Publication number 20240126457
- Publication date Apr 18, 2024
- Apple Inc.
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bandwidth-Aware Fabric Traffic Shaping
- Publication number 20230325086
- Publication date Oct 12, 2023
- Apple Inc.
- Anjana Subramanian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pixel Array and Touch Array Crosstalk Mitigation Systems and Methods
- Publication number 20230093204
- Publication date Mar 23, 2023
- Apple Inc.
- Salman Latif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GUARANTEED REAL-TIME CACHE CARVEOUT FOR DISPLAYED IMAGE PROCESSING...
- Publication number 20230081746
- Publication date Mar 16, 2023
- Apple Inc.
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Allocation of Cache Memory as RAM
- Publication number 20230067307
- Publication date Mar 2, 2023
- Apple Inc.
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Interface Circuit
- Publication number 20230064369
- Publication date Mar 2, 2023
- Apple Inc.
- Rohit K. Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Communication Channels with both Shared and Independent Resources
- Publication number 20230064187
- Publication date Mar 2, 2023
- Apple Inc.
- Rohit K. Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Allocation of a Buffer Located in System Memory into a Cache Memory
- Publication number 20230062917
- Publication date Mar 2, 2023
- Apple Inc.
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION AWARE SOC MEMORY CACHE PARTITIONING
- Publication number 20210034527
- Publication date Feb 4, 2021
- Apple Inc.
- Wolfgang H. Klingauf
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-OVERHEAD DEBUG ARCHITECTURE USING A SPECULATIVE, CONCURRENT & D...
- Publication number 20160202320
- Publication date Jul 14, 2016
- Samsung Electronics Co., Ltd.
- Rohit NATARAJAN
- G01 - MEASURING TESTING
Information Patent Application
MEMORY ARBITRATION TO ENSURE LOW LATENCY FOR HIGH PRIORITY MEMORY R...
- Publication number 20110246688
- Publication date Oct 6, 2011
- IRWIN VAZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMOR...
- Publication number 20090132773
- Publication date May 21, 2009
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method to merge and align data from distributed memor...
- Publication number 20060149872
- Publication date Jul 6, 2006
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory controller with command queue look-ahead
- Publication number 20050246481
- Publication date Nov 3, 2005
- Natarajan Rohit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Command scheduling for dual-data-rate two (DDR2) memory devices
- Publication number 20050204111
- Publication date Sep 15, 2005
- Rohit Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus utilizing non-uniformly distributed DRAM confi...
- Publication number 20050144413
- Publication date Jun 30, 2005
- Chen-Chi Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Packet assembly
- Publication number 20050135353
- Publication date Jun 23, 2005
- Prashant R. Chandra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory controller
- Publication number 20050135367
- Publication date Jun 23, 2005
- Prashant R. Chandra
- G06 - COMPUTING CALCULATING COUNTING

Natarajan Rohit

Person

Patents Grantslast 30 patents

Bandwidth-aware fabric traffic shaping

Allocation of a buffer located in system memory into a cache memory

Pixel array and touch array crosstalk mitigation systems and methods

Guaranteed real-time cache carveout for displayed image processing...

Communication channels with both shared and independent resources

Configurable interface circuit

Dynamic allocation of cache memory as RAM

Application aware SoC memory cache partitioning

Low-overhead debug architecture using a speculative, concurrent and...

Apparatus and method to merge and align data from distributed memor...

Apparatus and method to merge and align data from distributed memor...

Memory controller with command queue look-ahead

Method and apparatus utilizing non-uniformly distributed DRAM confi...

Memory controller for padding and stripping data in response to rea...

Packet assembly

Patents Applicationslast 30 patents

Dynamic Allocation of Cache Memory as RAM

Bandwidth-Aware Fabric Traffic Shaping

Pixel Array and Touch Array Crosstalk Mitigation Systems and Methods

GUARANTEED REAL-TIME CACHE CARVEOUT FOR DISPLAYED IMAGE PROCESSING...

Dynamic Allocation of Cache Memory as RAM

Configurable Interface Circuit

Communication Channels with both Shared and Independent Resources

Allocation of a Buffer Located in System Memory into a Cache Memory

APPLICATION AWARE SOC MEMORY CACHE PARTITIONING

LOW-OVERHEAD DEBUG ARCHITECTURE USING A SPECULATIVE, CONCURRENT & D...

MEMORY ARBITRATION TO ENSURE LOW LATENCY FOR HIGH PRIORITY MEMORY R...

APPARATUS AND METHOD TO MERGE AND ALIGN DATA FROM DISTRIBUTED MEMOR...

Apparatus and method to merge and align data from distributed memor...

Memory controller with command queue look-ahead

Command scheduling for dual-data-rate two (DDR2) memory devices

Method and apparatus utilizing non-uniformly distributed DRAM confi...

Packet assembly

Memory controller