Natarajan Viswanathan

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hierarchically-aware buffering for clock structures
- Patent number 12,321,193
- Issue date Jun 3, 2025
- Cadence Design Systems, Inc.
- Yi-Xiao Ding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning based clustering for clock tree synthesis
- Patent number 11,645,441
- Issue date May 9, 2023
- Cadence Design Systems, Inc.
- Bentian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Grouping cells in cell library based on clustering
- Patent number 11,625,525
- Issue date Apr 11, 2023
- Cadence Design Systems, Inc.
- Zhuo Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine-learning based prediction method for iterative clustering d...
- Patent number 11,244,099
- Issue date Feb 8, 2022
- Cadence Design Systems, Inc.
- Bentian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic weighting scheme for local cluster refinement
- Patent number 11,188,702
- Issue date Nov 30, 2021
- Cadence Design Systems, Inc.
- Bentian Jiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying route topology to fix clock tree violations
- Patent number 10,963,617
- Issue date Mar 30, 2021
- Cadence Design Systems, Inc.
- Andrew Mark Chapman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Large cluster persistence during placement optimization of integrat...
- Patent number 10,685,160
- Issue date Jun 16, 2020
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Region aware clustering
- Patent number 10,402,522
- Issue date Sep 3, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Balanced scaled-load clustering
- Patent number 10,318,693
- Issue date Jun 11, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local cluster refinement
- Patent number 10,289,797
- Issue date May 14, 2019
- Cadence Design Systems, Inc.
- Natarajan Viswanathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Large cluster persistence during placement optimization of integrat...
- Patent number 10,140,409
- Issue date Nov 27, 2018
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Element placement in circuit design based on preferred location
- Patent number 9,524,363
- Issue date Dec 20, 2016
- GLOBALFOUNDRIES Inc.
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Large cluster persistence during placement optimization of integrat...
- Patent number 9,495,501
- Issue date Nov 15, 2016
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alignment net insertion for straightening the datapath in a force-d...
- Patent number 9,251,306
- Issue date Feb 2, 2016
- GLOBALFOUNDRIES Inc.
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boundary latch and logic placement to satisfy timing constraints
- Patent number 9,098,669
- Issue date Aug 4, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structured placement of latches/flip-flops to minimize clock power...
- Patent number 8,954,912
- Issue date Feb 10, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of structured nets
- Patent number 8,793,636
- Issue date Jul 29, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-placement cell shifting
- Patent number 8,782,584
- Issue date Jul 15, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Separate refinement of local wirelength and local module density in...
- Patent number 8,769,457
- Issue date Jul 1, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic design automation object placement with partially region...
- Patent number 8,683,411
- Issue date Mar 25, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latch clustering with proximity to local clock buffers
- Patent number 8,677,299
- Issue date Mar 18, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock optimization with local clock buffer control optimization
- Patent number 8,667,441
- Issue date Mar 4, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Local objective optimization in global placement of an integrated c...
- Patent number 8,595,675
- Issue date Nov 26, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Datapath placement using tiered assignment
- Patent number 8,589,848
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post-placement cell shifting
- Patent number 8,495,534
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-patterning lithography aware cell placement in integrated cir...
- Patent number 8,495,548
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Kanak Behari Agarwal
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Latch clustering with proximity to local clock buffers
- Patent number 8,458,634
- Issue date Jun 4, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Alignment net insertion for straightening the datapath in a force-d...
- Patent number 8,453,093
- Issue date May 28, 2013
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accuracy pin-slew mode for gate delay calculation
- Patent number 8,418,108
- Issue date Apr 9, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental timing optimization and placement
- Patent number 8,347,249
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRAT...
- Publication number 20190026418
- Publication date Jan 24, 2019
- International Business Machines Corporation
- MYUNG-CHUL KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRAT...
- Publication number 20170220722
- Publication date Aug 3, 2017
- International Business Machines Corporation
- MYUNG-CHUL KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS
- Publication number 20150199465
- Publication date Jul 16, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER...
- Publication number 20140149957
- Publication date May 29, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN...
- Publication number 20140007036
- Publication date Jan 2, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-PLACEMENT CELL SHIFTING
- Publication number 20130346938
- Publication date Dec 26, 2013
- International Business Machines Corporation
- Charles J Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION
- Publication number 20130326455
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATAPATH PLACEMENT USING TIERED ASSIGNMENT
- Publication number 20130283225
- Publication date Oct 24, 2013
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-D...
- Publication number 20130205272
- Publication date Aug 8, 2013
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-D...
- Publication number 20130097573
- Publication date Apr 18, 2013
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIR...
- Publication number 20130086543
- Publication date Apr 4, 2013
- International Business Machines Corporation
- Kanak Behari Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION
- Publication number 20120324409
- Publication date Dec 20, 2012
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN
- Publication number 20120297355
- Publication date Nov 22, 2012
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement of Structured Nets
- Publication number 20120266124
- Publication date Oct 18, 2012
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Optimization with Local Clock Buffer Control Optimization
- Publication number 20120124539
- Publication date May 17, 2012
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS
- Publication number 20120110532
- Publication date May 3, 2012
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC DESIGN AUTOMATION OBJECT PLACEMENT WITH PARTIALLY REGION...
- Publication number 20120054708
- Publication date Mar 1, 2012
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETAILED ROUTABILITY BY CELL PLACEMENT
- Publication number 20110302545
- Publication date Dec 8, 2011
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-PLACEMENT CELL SHIFTING
- Publication number 20110302544
- Publication date Dec 8, 2011
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL TIMING OPTIMIZATION AND PLACEMENT
- Publication number 20100257498
- Publication date Oct 7, 2010
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Legalization of VLSI circuit placement with blockages using hierarc...
- Publication number 20090271752
- Publication date Oct 29, 2009
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES...
- Publication number 20080282213
- Publication date Nov 13, 2008
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES...
- Publication number 20080066037
- Publication date Mar 13, 2008
- INTERNATIONAL BUSINESS MACHINES COMPANY
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING

Natarajan Viswanathan

Person

Patents Grantslast 30 patents

Hierarchically-aware buffering for clock structures

Machine-learning based clustering for clock tree synthesis

Grouping cells in cell library based on clustering

Machine-learning based prediction method for iterative clustering d...

Dynamic weighting scheme for local cluster refinement

Modifying route topology to fix clock tree violations

Large cluster persistence during placement optimization of integrat...

Region aware clustering

Balanced scaled-load clustering

Local cluster refinement

Large cluster persistence during placement optimization of integrat...

Element placement in circuit design based on preferred location

Large cluster persistence during placement optimization of integrat...

Alignment net insertion for straightening the datapath in a force-d...

Boundary latch and logic placement to satisfy timing constraints

Structured placement of latches/flip-flops to minimize clock power...

Placement of structured nets

Post-placement cell shifting

Separate refinement of local wirelength and local module density in...

Electronic design automation object placement with partially region...

Latch clustering with proximity to local clock buffers

Clock optimization with local clock buffer control optimization

Local objective optimization in global placement of an integrated c...

Datapath placement using tiered assignment

Post-placement cell shifting

Multi-patterning lithography aware cell placement in integrated cir...

Latch clustering with proximity to local clock buffers

Alignment net insertion for straightening the datapath in a force-d...

Accuracy pin-slew mode for gate delay calculation

Incremental timing optimization and placement

Patents Applicationslast 30 patents

LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRAT...

LARGE CLUSTER PERSISTENCE DURING PLACEMENT OPTIMIZATION OF INTEGRAT...

BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS

STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER...

SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN...

POST-PLACEMENT CELL SHIFTING

ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION

DATAPATH PLACEMENT USING TIERED ASSIGNMENT

ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-D...

ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-D...

MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIR...

ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION

WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN

Placement of Structured Nets

Clock Optimization with Local Clock Buffer Control Optimization

LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS

ELECTRONIC DESIGN AUTOMATION OBJECT PLACEMENT WITH PARTIALLY REGION...

DETAILED ROUTABILITY BY CELL PLACEMENT

POST-PLACEMENT CELL SHIFTING

INCREMENTAL TIMING OPTIMIZATION AND PLACEMENT

Legalization of VLSI circuit placement with blockages using hierarc...

METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES...

METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES...