Nathan Sheeley

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Skip buffer splitting
- Patent number 12,045,591
- Issue date Jul 23, 2024
- SambaNova Systems, Inc.
- Nathan Sheeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tensor partitioning and partition access order
- Patent number 11,561,925
- Issue date Jan 24, 2023
- SambaNova Systems, Inc.
- Raghu Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse matrix multiplier in hardware and a reconfigurable data proc...
- Patent number 11,443,014
- Issue date Sep 13, 2022
- SambaNova Systems, Inc.
- Mingran Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-headed multi-buffer for buffering data for processing
- Patent number 11,366,783
- Issue date Jun 21, 2022
- SambaNova Systems, Inc.
- Raghu Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tensor partitioning and partition access order
- Patent number 11,204,889
- Issue date Dec 21, 2021
- SambaNova Systems, Inc.
- Raghu Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware mechanism to mitigate stalling of a processor core
- Patent number 10,740,102
- Issue date Aug 11, 2020
- Oracle International Corporation
- Munsefar Khaleque
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for piecewise hierarchical sequential verification
- Patent number 8,448,107
- Issue date May 21, 2013
- Apple Inc.
- Nathan Francis Sheeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Macroblock cache
- Patent number 7,965,773
- Issue date Jun 21, 2011
- Advanced Micro Devices, Inc.
- Erik Schlanger
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
COARSE-GRAINED RECONFIGURABLE PROCESSOR ARRAY WITH OPTIMIZED BUFFERS
- Publication number 20240370240
- Publication date Nov 7, 2024
- SambaNova Systems, Inc.
- Nathan Francis SHEELEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffer Fusion and Layout Optimization
- Publication number 20230409233
- Publication date Dec 21, 2023
- SambaNova Systems, Inc.
- Nathan Francis SHEELEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Skip Buffer Splitting
- Publication number 20230385043
- Publication date Nov 30, 2023
- SambaNova Systems, Inc.
- Nathan SHEELEY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Tensor Partitioning and Partition Access Order
- Publication number 20220309029
- Publication date Sep 29, 2022
- SambaNova Systems, Inc.
- Raghu PRABHAKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE MECHANISM TO MITIGATE STALLING OF A PROCESSOR CORE
- Publication number 20180246720
- Publication date Aug 30, 2018
- Munsefar Khaleque
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method For Piecewise Hierarchical Sequential Verification
- Publication number 20110214096
- Publication date Sep 1, 2011
- Intrinsity, Inc.
- Nathan Francis Sheeley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic synchronizer simulation
- Publication number 20070129923
- Publication date Jun 7, 2007
- Advanced Micro Devices, Inc.
- Mark Langer
- G06 - COMPUTING CALCULATING COUNTING

Nathan Sheeley

Person

Patents Grantslast 30 patents

Skip buffer splitting

Tensor partitioning and partition access order

Sparse matrix multiplier in hardware and a reconfigurable data proc...

Multi-headed multi-buffer for buffering data for processing

Tensor partitioning and partition access order

Hardware mechanism to mitigate stalling of a processor core

Method for piecewise hierarchical sequential verification

Macroblock cache

Patents Applicationslast 30 patents

COARSE-GRAINED RECONFIGURABLE PROCESSOR ARRAY WITH OPTIMIZED BUFFERS

Buffer Fusion and Layout Optimization

Skip Buffer Splitting

Tensor Partitioning and Partition Access Order

HARDWARE MECHANISM TO MITIGATE STALLING OF A PROCESSOR CORE

Method For Piecewise Hierarchical Sequential Verification

Dynamic synchronizer simulation