Nathaniel R. Chadwick

Person

Lowell, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methodology of grading reliability and performance of chips across...
- Patent number 9,575,115
- Issue date Feb 21, 2017
- GLOBALFOUNDRIES Inc.
- Nathaniel R. Chadwick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power gating and clock gating in wiring levels
- Patent number 9,520,876
- Issue date Dec 13, 2016
- International Business Machines Corporation
- Nathaniel R. Chadwick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Stress balancing of circuits
- Patent number 9,472,269
- Issue date Oct 18, 2016
- GLOBALFOUNDRIES Inc.
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Light activated test connections
- Patent number 9,437,670
- Issue date Sep 6, 2016
- GLOBALFOUNDRIES Inc.
- Nathaniel R. Chadwick
- G01 - MEASURING TESTING
Information Patent Grant
Circuit design for balanced logic stress
- Patent number 9,383,767
- Issue date Jul 5, 2016
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design for balanced logic stress
- Patent number 9,250,645
- Issue date Feb 2, 2016
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thermal energy dissipation using backside thermoelectric devices
- Patent number 9,099,427
- Issue date Aug 4, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Determining chip burn-in workload using emulated application condition
- Patent number 8,943,458
- Issue date Jan 27, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CIRCUIT DESIGN FOR BALANCED LOGIC STRESS
- Publication number 20150253807
- Publication date Sep 10, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN FOR BALANCED LOGIC STRESS
- Publication number 20150253808
- Publication date Sep 10, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRESS BALANCING OF CIRCUITS
- Publication number 20150228357
- Publication date Aug 13, 2015
- International Business Machines Corporation
- Igor ARSOVSKI
- G11 - INFORMATION STORAGE
Information Patent Application
THERMAL ENERGY DISSIPATION USING BACKSIDE THERMOELECTRIC DEVICES
- Publication number 20150115431
- Publication date Apr 30, 2015
- International Business Machines Corporation
- Nathaniel R. Chadwick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR RELATING TEST TIME AND ESCAPE RATE FOR MULTIVARIATE ISSUE
- Publication number 20150051869
- Publication date Feb 19, 2015
- International Business Machines Corporation
- Jennifer E. Appleyard
- G01 - MEASURING TESTING
Information Patent Application
LIGHT ACTIVATED TEST CONNECTIONS
- Publication number 20140145747
- Publication date May 29, 2014
- International Business Machines Corporation
- Nathaniel R. CHADWICK
- G01 - MEASURING TESTING
Information Patent Application
METHODOLOGY OF GRADING RELIABILITY AND PERFORMANCE OF CHIPS ACROSS...
- Publication number 20140107822
- Publication date Apr 17, 2014
- International Business Machines Corporation
- Nathaniel R. Chadwick
- G01 - MEASURING TESTING

Nathaniel R. Chadwick

Person

Patents Grantslast 30 patents

Methodology of grading reliability and performance of chips across...

Power gating and clock gating in wiring levels

Stress balancing of circuits

Light activated test connections

Circuit design for balanced logic stress

Circuit design for balanced logic stress

Thermal energy dissipation using backside thermoelectric devices

Determining chip burn-in workload using emulated application condition

Patents Applicationslast 30 patents

CIRCUIT DESIGN FOR BALANCED LOGIC STRESS

CIRCUIT DESIGN FOR BALANCED LOGIC STRESS

STRESS BALANCING OF CIRCUITS

THERMAL ENERGY DISSIPATION USING BACKSIDE THERMOELECTRIC DEVICES

METHOD FOR RELATING TEST TIME AND ESCAPE RATE FOR MULTIVARIATE ISSUE

LIGHT ACTIVATED TEST CONNECTIONS

METHODOLOGY OF GRADING RELIABILITY AND PERFORMANCE OF CHIPS ACROSS...