Naveen Bhoria

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 12,271,314
- Issue date Apr 8, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-up table initialize
- Patent number 12,242,852
- Issue date Mar 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 12,197,331
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for inflight data forwarding and invalidation...
- Patent number 12,141,073
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-up table read
- Patent number 12,093,690
- Issue date Sep 17, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aliased mode for cache controller
- Patent number 12,086,064
- Issue date Sep 10, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tag update bus for updated coherence state
- Patent number 12,056,051
- Issue date Aug 6, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level cache security
- Patent number 12,038,840
- Issue date Jul 16, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,007,907
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache that supports draining write-miss entries
- Patent number 12,001,345
- Issue date Jun 4, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look-up table write
- Patent number 11,960,891
- Issue date Apr 16, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce read-modify-write cycles for non-al...
- Patent number 11,940,929
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 11,940,930
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 11,886,353
- Issue date Jan 30, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 11,868,272
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 11,816,032
- Issue date Nov 14, 2023
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20250147888
- Publication date May 8, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR INFLIGHT DATA FORWARDING AND INVALIDATION...
- Publication number 20250028645
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20250028551
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALIASED MODE FOR CACHE CONTROLLER
- Publication number 20250021481
- Publication date Jan 16, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOK-UP TABLE READ
- Publication number 20240403054
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR INFLIGHT DATA FORWARDING AND INVALIDATION...
- Publication number 20240362166
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL CACHE SECURITY
- Publication number 20240320154
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20240193098
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOOK-UP TABLE WRITE
- Publication number 20240176620
- Publication date May 30, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20240143516
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20240104026
- Publication date Mar 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240095164
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE SIZE CHANGE
- Publication number 20240095169
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS
- Publication number 20240078190
- Publication date Mar 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20240045803
- Publication date Feb 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLIED FENCE ON STREAM OPEN
- Publication number 20240036867
- Publication date Feb 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING

Naveen Bhoria

Person

Patents Grantslast 30 patents

Write merging on stores with different privilege levels

Cache size change

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

Look-up table initialize

Atomic compare and swap in a coherent cache system

Aggressive write flush scheme for a victim cache

Methods and apparatus to reduce bank pressure using aggressive writ...

Hardware coherence signaling protocol

Fully pipelined read-modify-write support

Methods and apparatus for allocation in a victim cache system

Methods and apparatus for read-modify-write support in multi-banked...

Global coherence operations

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Methods and apparatus for inflight data forwarding and invalidation...

Methods and apparatus for eviction in dual datapath victim cache sy...

Look-up table read

Aliased mode for cache controller

Methods and apparatus to facilitate read-modify-write support in a...

Tag update bus for updated coherence state

Multi-level cache security

Victim cache with write miss merging

Victim cache that supports draining write-miss entries

Look-up table write

Methods and apparatus to reduce read-modify-write cycles for non-al...

Methods and apparatus to facilitate atomic operations in victim cache

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for allocation in a victim cache system

Cache size change

Patents Applicationslast 30 patents

HARDWARE COHERENCE SIGNALING PROTOCOL

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

METHODS AND APPARATUS FOR INFLIGHT DATA FORWARDING AND INVALIDATION...

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

GLOBAL COHERENCE OPERATIONS

ALIASED MODE FOR CACHE CONTROLLER

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

LOOK-UP TABLE READ

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

METHODS AND APPARATUS FOR INFLIGHT DATA FORWARDING AND INVALIDATION...

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

MULTI-LEVEL CACHE SECURITY

VICTIM CACHE WITH WRITE MISS MERGING

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

LOOK-UP TABLE WRITE

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

CACHE SIZE CHANGE

WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS

HARDWARE COHERENCE SIGNALING PROTOCOL

IMPLIED FENCE ON STREAM OPEN