Naveen Chandra Srivastava

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Kanpur, IN

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Patents Grantslast 30 patents

Information Patent Grant
Reducing the load on the bitlines of a ROM bitcell array
- Patent number 9,898,568
- Issue date Feb 20, 2018
- Advanced Micro Devices, Inc.
- Naveen Chandra Srivastava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a cut mask to form spaces representing spacing violations in...
- Patent number 9,710,589
- Issue date Jul 18, 2017
- Advanced Micro Devices, Inc.
- Kalpeshkumar Girishchandra Dave
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method and system for characterizing an integrated circuit design
- Patent number 7,900,174
- Issue date Mar 1, 2011
- Interra Systems Inc
- Rajiv Shankar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
REDUCING THE LOAD ON THE BITLINES OF A ROM BITCELL ARRAY
- Publication number 20160378898
- Publication date Dec 29, 2016
- Advanced Micro Devices, Inc.
- Naveen Chandra Srivastava
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR AREA OPTIMIZATION
- Publication number 20160378899
- Publication date Dec 29, 2016
- Advanced Micro Devices, Inc.
- Kalpeshkumar Girishchandra Dave
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for characterizing an integrated circuit design
- Publication number 20090288055
- Publication date Nov 19, 2009
- Rajiv Shankar
- G06 - COMPUTING CALCULATING COUNTING