Navneet Dour

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Duty cycle correction system and low dropout (LDO) regulator based...
- Patent number 11,722,128
- Issue date Aug 8, 2023
- Intel Corporation
- Aaron Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Duty cycle correction system and low dropout (LDO) regulator based...
- Patent number 11,070,200
- Issue date Jul 20, 2021
- Intel Corporation
- Aaron Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically programmable memory test traffic router
- Patent number 11,042,315
- Issue date Jun 22, 2021
- Intel Corporation
- Lakshminarayana Pappu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Platform debug and testing with secured hardware
- Patent number 10,613,955
- Issue date Apr 7, 2020
- Intel Corporation
- Lakshminarayana Pappu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extended synchronized clock
- Patent number 7,751,274
- Issue date Jul 6, 2010
- Intel Corporation
- Navneet Dour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wake-up circuit
- Patent number 7,746,135
- Issue date Jun 29, 2010
- Intel Corporation
- Jacob S. Schneider
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Calibrating integrating receivers for source synchronous protocol
- Patent number 7,602,859
- Issue date Oct 13, 2009
- Intel Corporation
- Roger K. Cheng
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus to calibrate DRAM on resistance (Ron) and on-d...
- Patent number 7,432,731
- Issue date Oct 7, 2008
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
PVT controller for programmable on die termination
- Patent number 7,403,034
- Issue date Jul 22, 2008
- Intel Corporation
- Navneet Dour
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for optimizing strobe to clock relationship
- Patent number 7,307,900
- Issue date Dec 11, 2007
- Intel Corporation
- Joe Salmon
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for PVT controller for programmable on die ter...
- Patent number 7,020,818
- Issue date Mar 28, 2006
- Intel Corporation
- Navneet Dour
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Slew rate at buffers by isolating predriver from driver
- Patent number 7,012,451
- Issue date Mar 14, 2006
- Intel Corporation
- Adhiveeraraghavan Srikanth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamically activated memory controller data termination
- Patent number 7,009,894
- Issue date Mar 7, 2006
- Intel Corporation
- Anoop Mukker
- G11 - INFORMATION STORAGE
Information Patent Grant
Slew rate at buffers by isolating predriver from driver
- Patent number 6,617,891
- Issue date Sep 9, 2003
- Intel Corporation
- Adhiveeraraghavan Srikanth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Driver impedance control mechanism
- Patent number 6,563,337
- Issue date May 13, 2003
- Intel Corporation
- Navneet Dour
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
AC timings at the input buffer of source synchronous and common clo...
- Patent number 6,414,539
- Issue date Jul 2, 2002
- Intel Corporation
- Adhiveeraraghavan Srikanth
- G05 - CONTROLLING REGULATING
Information Patent Grant
Circuit for independent power-up sequencing of a multi-voltage chip
- Patent number 6,236,250
- Issue date May 22, 2001
- Intel Corporation
- Joseph H. Salmon
- G05 - CONTROLLING REGULATING

Patents Applicationslast 30 patents

Information Patent Application
DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED...
- Publication number 20210320652
- Publication date Oct 14, 2021
- Intel Corporation
- Aaron Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED...
- Publication number 20200106430
- Publication date Apr 2, 2020
- Intel Corporation
- Aaron Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY PROGRAMMABLE MEMORY TEST TRAFFIC ROUTER
- Publication number 20190042131
- Publication date Feb 7, 2019
- Intel Corporation
- Lakshminarayana PAPPU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLATFORM DEBUG AND TESTING WITH SECURED HARDWARE
- Publication number 20190042382
- Publication date Feb 7, 2019
- Intel Corporation
- Lakshminarayana PAPPU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAKE-UP CIRCUIT
- Publication number 20090085618
- Publication date Apr 2, 2009
- Jacob S. Schneider
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Extended synchronized clock
- Publication number 20080065922
- Publication date Mar 13, 2008
- Navneet Dour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to calibrate DRAM Ron and ODT values over PVT
- Publication number 20070007992
- Publication date Jan 11, 2007
- Kuljit S. Bains
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Calibrating integrating receivers for source synchronous protocol
- Publication number 20060245519
- Publication date Nov 2, 2006
- Roger K. Cheng
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Integrating receivers for source synchronous protocol
- Publication number 20060245473
- Publication date Nov 2, 2006
- Roger K. Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PVT controller for programmable on die termination
- Publication number 20060119381
- Publication date Jun 8, 2006
- Navneet Dour
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for optimizing strobe to clock relationship
- Publication number 20060114742
- Publication date Jun 1, 2006
- Joe Salmon
- G11 - INFORMATION STORAGE
Information Patent Application
Signal drive de-emphasis for memory bus
- Publication number 20060002482
- Publication date Jan 5, 2006
- Clinton Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for PVT controller for programmable on die ter...
- Publication number 20050194991
- Publication date Sep 8, 2005
- Navneet Dour
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and a method to adjust signal timing on a memory interface
- Publication number 20050190193
- Publication date Sep 1, 2005
- David E. Freker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ACTIVATED MEMORY CONTROLLER DATA TERMINATION
- Publication number 20050185480
- Publication date Aug 25, 2005
- Anoop Mukker
- G11 - INFORMATION STORAGE
Information Patent Application
Slew rate at buffers by isolating predriver from driver
- Publication number 20050013071
- Publication date Jan 20, 2005
- Adhiveeraraghavan Srikanth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Slew rate at buffers by isolating predriver from driver
- Publication number 20030058006
- Publication date Mar 27, 2003
- Adhiveeraraghavan Srikanth
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Driver impedance control mechanism
- Publication number 20030001611
- Publication date Jan 2, 2003
- Navneet Dour
- H03 - BASIC ELECTRONIC CIRCUITRY

Navneet Dour

Person

Patents Grantslast 30 patents

Duty cycle correction system and low dropout (LDO) regulator based...

Duty cycle correction system and low dropout (LDO) regulator based...

Dynamically programmable memory test traffic router

Platform debug and testing with secured hardware

Extended synchronized clock

Wake-up circuit

Calibrating integrating receivers for source synchronous protocol

Method and apparatus to calibrate DRAM on resistance (Ron) and on-d...

PVT controller for programmable on die termination

Method and apparatus for optimizing strobe to clock relationship

Method and apparatus for PVT controller for programmable on die ter...

Slew rate at buffers by isolating predriver from driver

Dynamically activated memory controller data termination

Slew rate at buffers by isolating predriver from driver

Driver impedance control mechanism

AC timings at the input buffer of source synchronous and common clo...

Circuit for independent power-up sequencing of a multi-voltage chip

Patents Applicationslast 30 patents

DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED...

DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED...

DYNAMICALLY PROGRAMMABLE MEMORY TEST TRAFFIC ROUTER

PLATFORM DEBUG AND TESTING WITH SECURED HARDWARE

WAKE-UP CIRCUIT

Extended synchronized clock

Method to calibrate DRAM Ron and ODT values over PVT

Calibrating integrating receivers for source synchronous protocol

Integrating receivers for source synchronous protocol

PVT controller for programmable on die termination

Method and apparatus for optimizing strobe to clock relationship

Signal drive de-emphasis for memory bus

Method and apparatus for PVT controller for programmable on die ter...

Apparatus and a method to adjust signal timing on a memory interface

DYNAMICALLY ACTIVATED MEMORY CONTROLLER DATA TERMINATION

Slew rate at buffers by isolating predriver from driver

Slew rate at buffers by isolating predriver from driver

Driver impedance control mechanism