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Navneet Kaushik
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Delhi, IN
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Patents Grants
last 30 patents
Information
Patent Grant
Test logic at register transfer level in an integrated circuit design
Patent number
10,192,013
Issue date
Jan 29, 2019
Cadence Design Systems, Inc.
Puneet Arora
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Memory built-in self-test logic in an integrated circuit design
Patent number
10,095,822
Issue date
Oct 9, 2018
Cadence Design Systems, Inc.
Navneet Kaushik
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus for testing error correction code (ECC) logic...
Patent number
9,865,362
Issue date
Jan 9, 2018
Cadence Design Systems, Inc.
Puneet Arora
G11 - INFORMATION STORAGE
Information
Patent Grant
Power domain aware insertion methods and designs for testing and re...
Patent number
9,640,280
Issue date
May 2, 2017
Cadence Design Systems, Inc.
Puneet Arora
G11 - INFORMATION STORAGE
Information
Patent Grant
Method and apparatus for optimizing memory-built-in-self test
Patent number
8,990,749
Issue date
Mar 24, 2015
Cadence Design Systems, Inc.
Puneet Arora
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Method and apparatus for optimizing memory-built-in-self test
Patent number
8,719,761
Issue date
May 6, 2014
Candence Design Systems, Inc.
Norman Card
G06 - COMPUTING CALCULATING COUNTING
Patents Applications
last 30 patents
Information
Patent Application
Method and Apparatus for Optimizing Memory-Built-In-Self Test
Publication number
20140089874
Publication date
Mar 27, 2014
Cadence Design Systems, Inc.
Norman Card
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Application
Method and Apparatus for Optimizing Memory-Built-In-Self Test
Publication number
20140089875
Publication date
Mar 27, 2014
Cadence Design Systems, Inc.
Puneet Arora
G06 - COMPUTING CALCULATING COUNTING