Nelson Wu

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Performance and reliability of processor store operation data trans...
- Patent number 12,141,071
- Issue date Nov 12, 2024
- International Business Machnes Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validation of store coherence relative to page translation invalida...
- Patent number 12,130,749
- Issue date Oct 29, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence validation using delayed fulfillment of L2 requests
- Patent number 12,118,355
- Issue date Oct 15, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validation of store coherence relative to page translation invalida...
- Patent number 11,620,235
- Issue date Apr 4, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pre-silicon chip model of extracted workload inner loop instruction...
- Patent number 11,501,046
- Issue date Nov 15, 2022
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
List insertion in test segments with non-naturally aligned data bou...
- Patent number 11,094,391
- Issue date Aug 17, 2021
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, system, and apparatus for stress testing memory translation...
- Patent number 11,061,821
- Issue date Jul 13, 2021
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for testing processor errors
- Patent number 10,748,637
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and apparatus for stress testing memory translation...
- Patent number 10,521,355
- Issue date Dec 31, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,489,261
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,481,991
- Issue date Nov 19, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
List insertion in test segments with non-naturally aligned data bou...
- Patent number 10,438,682
- Issue date Oct 8, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,169,185
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient testing of direct memory address translation
- Patent number 10,169,186
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PERFORMANCE AND RELIABILITY OF PROCESSOR STORE OPERATION DATA TRANS...
- Publication number 20240028518
- Publication date Jan 25, 2024
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HAZARD GENERATING FOR SPECULATIVE CORES IN A MICROPROCESSOR
- Publication number 20230195981
- Publication date Jun 22, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...
- Publication number 20230195649
- Publication date Jun 22, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE VALIDATION USING DELAYED FULFILLMENT OF L2 REQUESTS
- Publication number 20230122466
- Publication date Apr 20, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...
- Publication number 20230105945
- Publication date Apr 6, 2023
- International Business Machines Corporation
- Shakti Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRE-SILICON CHIP MODEL OF EXTRACTED WORKLOAD INNER LOOP INSTRUCTION...
- Publication number 20210303766
- Publication date Sep 30, 2021
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...
- Publication number 20200089621
- Publication date Mar 19, 2020
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Method for Testing Processor Errors
- Publication number 20200035319
- Publication date Jan 30, 2020
- International Business Machines Corporation
- Nelson Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...
- Publication number 20190287639
- Publication date Sep 19, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Application
LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...
- Publication number 20190198132
- Publication date Jun 27, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...
- Publication number 20190188146
- Publication date Jun 20, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION
- Publication number 20190050314
- Publication date Feb 14, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION
- Publication number 20190050315
- Publication date Feb 14, 2019
- International Business Machines Corporation
- Manoj Dusanapudi
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Performance and reliability of processor store operation data trans...

Validation of store coherence relative to page translation invalida...

Cache coherence validation using delayed fulfillment of L2 requests

Validation of store coherence relative to page translation invalida...

Pre-silicon chip model of extracted workload inner loop instruction...

List insertion in test segments with non-naturally aligned data bou...

Method, system, and apparatus for stress testing memory translation...

System and method for testing processor errors

Method, system, and apparatus for stress testing memory translation...

Efficient testing of direct memory address translation

Efficient testing of direct memory address translation

List insertion in test segments with non-naturally aligned data bou...

Efficient testing of direct memory address translation

Efficient testing of direct memory address translation

Patents Applicationslast 30 patents

PERFORMANCE AND RELIABILITY OF PROCESSOR STORE OPERATION DATA TRANS...

HAZARD GENERATING FOR SPECULATIVE CORES IN A MICROPROCESSOR

VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...

CACHE COHERENCE VALIDATION USING DELAYED FULFILLMENT OF L2 REQUESTS

VALIDATION OF STORE COHERENCE RELATIVE TO PAGE TRANSLATION INVALIDA...

PRE-SILICON CHIP MODEL OF EXTRACTED WORKLOAD INNER LOOP INSTRUCTION...

METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...

System and Method for Testing Processor Errors

LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...

LIST INSERTION IN TEST SEGMENTS WITH NON-NATURALLY ALIGNED DATA BOU...

METHOD, SYSTEM, AND APPARATUS FOR STRESS TESTING MEMORY TRANSLATION...

EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION

EFFICIENT TESTING OF DIRECT MEMORY ADDRESS TRANSLATION