Nga-Ching Wong

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for manufacturing a double bitline implant
- Patent number 7,232,729
- Issue date Jun 19, 2007
- Spansion LLC
- Nga-Ching Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with high conductivity region using shallow tr...
- Patent number 7,208,382
- Issue date Apr 24, 2007
- Advanced Micro Devices, Inc.
- Jeffrey P. Erhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
LDC implant for mirrorbit to improve Vt roll-off and form sharper j...
- Patent number 7,176,113
- Issue date Feb 13, 2007
- Spansion LLC
- Nga-Ching Alan Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric memory cell structure with counter doped channel region
- Patent number 7,151,292
- Issue date Dec 19, 2006
- Spansion LLC
- Nga-Ching Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method to reduce drain induced barrier lowering
- Patent number 7,067,381
- Issue date Jun 27, 2006
- Advanced Micro Devices, Inc.
- Timothy Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lateral doped channel
- Patent number 7,049,188
- Issue date May 23, 2006
- Advanced Micro Devices, Inc.
- Nga-Ching Wong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate bias for programming non-volatile memory
- Patent number 7,023,740
- Issue date Apr 4, 2006
- Advanced Micro Devices, Inc.
- Nga-Ching Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage transistor scaling tilt ion implant method
- Patent number 7,011,998
- Issue date Mar 14, 2006
- Advanced Micro Devices, Inc.
- Dong-Hyuk Ju
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pocket implant for complementary bit disturb improvement and chargi...
- Patent number 6,958,272
- Issue date Oct 25, 2005
- Advanced Micro Devices, Inc.
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a dielectric spacer in a non-volatile memory device
- Patent number 6,908,816
- Issue date Jun 21, 2005
- Advanced Micro Devices, Inc.
- Timothy Thurgate
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing drain induced barrier lowering in a memory device
- Patent number 6,833,297
- Issue date Dec 21, 2004
- Advanced Micro Devices, Inc.
- Richard M. Fastow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for measuring source and drain junction depth in silicon on...
- Patent number 6,475,816
- Issue date Nov 5, 2002
- Advanced Micro Devices, Inc.
- Concetta Riccobene
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TR...
- Publication number 20070166938
- Publication date Jul 19, 2007
- Advanced Micro Devices, Inc.
- Jeffrey P. Erhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Pocket implant for complementary bit disturb improvement and chargi...
- Publication number 20050153508
- Publication date Jul 14, 2005
- Emmanuil H. Lingunis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Lateral doped channel
- Publication number 20040102026
- Publication date May 27, 2004
- Nga-Ching Wong
- H01 - BASIC ELECTRIC ELEMENTS

Nga-Ching Wong

Person

Patents Grantslast 30 patents

Method for manufacturing a double bitline implant

Semiconductor device with high conductivity region using shallow tr...

LDC implant for mirrorbit to improve Vt roll-off and form sharper j...

Dielectric memory cell structure with counter doped channel region

Structure and method to reduce drain induced barrier lowering

Lateral doped channel

Substrate bias for programming non-volatile memory

High voltage transistor scaling tilt ion implant method

Pocket implant for complementary bit disturb improvement and chargi...

Method for forming a dielectric spacer in a non-volatile memory device

Method for reducing drain induced barrier lowering in a memory device

Method for measuring source and drain junction depth in silicon on...

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE WITH HIGH CONDUCTIVITY REGION USING SHALLOW TR...

Pocket implant for complementary bit disturb improvement and chargi...

Lateral doped channel