Nicholas J. Richardson

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Estimating an error rate associated with memory
- Patent number 11,334,413
- Issue date May 17, 2022
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High throughput bit correction of data inside a word buffer for a p...
- Patent number 10,846,175
- Issue date Nov 24, 2020
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Updating reliability data
- Patent number 10,628,256
- Issue date Apr 21, 2020
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Estimating an error rate associated with memory
- Patent number 10,572,338
- Issue date Feb 25, 2020
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Progressive effort decoder architecture
- Patent number 10,498,367
- Issue date Dec 3, 2019
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Area efficient implementation of a product code error correcting co...
- Patent number 10,439,648
- Issue date Oct 8, 2019
- Micron Technology, Inc.
- Patrick R. Khayat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for layer-by-layer error correction
- Patent number 10,326,479
- Issue date Jun 18, 2019
- Micron Technology, Inc.
- Mustafa N. Kaynak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Updating reliability data
- Patent number 10,191,804
- Issue date Jan 29, 2019
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Estimating an error rate associated with memory
- Patent number 10,061,643
- Issue date Aug 28, 2018
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Progressive effort decoder architecture
- Patent number 9,654,144
- Issue date May 16, 2017
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Updating reliability data with a variable node and check nodes
- Patent number 9,612,903
- Issue date Apr 4, 2017
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Estimating an error rate associated with memory
- Patent number 9,558,064
- Issue date Jan 31, 2017
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method using hashing for efficiently implementing an...
- Patent number 8,295,286
- Issue date Oct 23, 2012
- STMicroelectronics, Inc.
- Suresh Rajgopal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Channel constrained code aware interleaver
- Patent number 8,055,973
- Issue date Nov 8, 2011
- STMicroelectronics, Inc.
- Shayan Srinivasa Garani
- G11 - INFORMATION STORAGE
Information Patent Grant
Mechanism to reduce lookup latency in a pipelined hardware implemen...
- Patent number 7,924,839
- Issue date Apr 12, 2011
- STMicroelectronics, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for providing cascaded trie-based network packet...
- Patent number 7,895,213
- Issue date Feb 22, 2011
- STMicroelectronics, Inc.
- Nicholas J. Richardson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method of using fully configurable memory, multi-stag...
- Patent number 7,782,853
- Issue date Aug 24, 2010
- STMicroelectronics, Inc.
- Lun Bin Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for path compression optimization in a pipelined...
- Patent number 7,715,392
- Issue date May 11, 2010
- STMicroelectronics, Inc.
- Lun Bin Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for handling register dependency in a stack-based...
- Patent number 7,496,734
- Issue date Feb 24, 2009
- STMicroelectronics, Inc.
- Nicholas J. Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for providing cascaded trie-based network packet...
- Patent number 7,299,227
- Issue date Nov 20, 2007
- STMicroelectronics, Inc.
- Nicholas J. Richardson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for increasing storage capacity in a multi-bit trie-based ha...
- Patent number 7,162,481
- Issue date Jan 9, 2007
- STMicroelectronics, Inc.
- Nicholas Julian Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for increasing average storage capacity in a bit-mapped tree...
- Patent number 7,099,881
- Issue date Aug 29, 2006
- STMicroelectronics, Inc.
- Nicholas Julian Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction fetch buffer stack fold decoder for generating foldable...
- Patent number 6,832,307
- Issue date Dec 14, 2004
- STMicroelectronics, Inc.
- Nicholas J. Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor cache system with parity protection and method of operation
- Patent number 6,507,928
- Issue date Jan 14, 2003
- STMicroelectronics, Inc.
- Nicholas J. Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus interface unit having multipurpose transaction buffer
- Patent number 6,205,506
- Issue date Mar 20, 2001
- STMicroelectronics, Inc.
- Nicholas J. Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus interface unit having dual purpose transaction buffer
- Patent number 6,101,568
- Issue date Aug 8, 2000
- STMicroelectronics, Inc.
- Nicholas J. Richardson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY
- Publication number 20200159616
- Publication date May 21, 2020
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH THROUGHPUT BIT CORRECTION OF DATA INSIDE A WORD BUFFER FOR A P...
- Publication number 20190310912
- Publication date Oct 10, 2019
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA EFFICIENT IMPLEMENTATION OF A PRODUCT CODE ERROR CORRECTING CO...
- Publication number 20190312600
- Publication date Oct 10, 2019
- Micron Technology, Inc.
- Patrick R. Khayat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UPDATING RELIABILITY DATA
- Publication number 20190146866
- Publication date May 16, 2019
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY
- Publication number 20180341546
- Publication date Nov 29, 2018
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR LAYER-BY-LAYER ERROR CORRECTION
- Publication number 20180013451
- Publication date Jan 11, 2018
- Micron Technology, Inc.
- Mustafa N. Kaynak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRESSIVE EFFORT DECODER ARCHITECTURE
- Publication number 20170222663
- Publication date Aug 3, 2017
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY
- Publication number 20170097859
- Publication date Apr 6, 2017
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UPDATING RELIABILITY DATA
- Publication number 20160259686
- Publication date Sep 8, 2016
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY
- Publication number 20160218740
- Publication date Jul 28, 2016
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRESSIVE EFFORT DECODER ARCHITECTURE
- Publication number 20160094247
- Publication date Mar 31, 2016
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
UPDATING RELIABILITY DATA
- Publication number 20140108883
- Publication date Apr 17, 2014
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHANNEL CONSTRAINED CODE AWARE INTERLEAVER
- Publication number 20100313083
- Publication date Dec 9, 2010
- STMicroelectronics, Inc.
- Shayan Srinivasa Garani
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and system for providing cascaded trie-based network packet...
- Publication number 20080046428
- Publication date Feb 21, 2008
- STMicroelectronics, Inc.
- Nicholas J. Richardson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus and method using hashing for efficiently implementing an...
- Publication number 20050141519
- Publication date Jun 30, 2005
- STMicroelectronics, Inc.
- Suresh Rajgopal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and system for providing cascaded trie-based network packet...
- Publication number 20050055339
- Publication date Mar 10, 2005
- STMicroelectronics, Inc.
- Nicholas J. Richardson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for path compression optimization in a pipelined...
- Publication number 20040114587
- Publication date Jun 17, 2004
- STMicroelectronics, Inc.
- Lun Bin Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Mechanism to reduce lookup latency in a pipelined hardware implemen...
- Publication number 20040111395
- Publication date Jun 10, 2004
- STMicroelectronics, Inc.
- Suresh Rajgopal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and method of using fully configurable memory, multi-stag...
- Publication number 20040109451
- Publication date Jun 10, 2004
- STMicroelectronics, Inc.
- Lun Bin Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method for increasing storage capacity in a multi-bit trie-based ha...
- Publication number 20040111440
- Publication date Jun 10, 2004
- STMicroelectronics, Inc.
- Nicholas Julian Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for increasing average storage capacity in a bit-mapped tree...
- Publication number 20040111439
- Publication date Jun 10, 2004
- STMicroelectronics, Inc.
- Nicholas Julian Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Progressive instruction folding in a processor with fast instructio...
- Publication number 20030046519
- Publication date Mar 6, 2003
- Nicholas J. Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINED NON-BLOCKING LEVEL TWO CACHE SYSTEM WITH INHERENT TRANSAC...
- Publication number 20020069326
- Publication date Jun 6, 2002
- NICHOLAS J. RICHARDSON
- G06 - COMPUTING CALCULATING COUNTING

Nicholas J. Richardson

Person

Patents Grantslast 30 patents

Estimating an error rate associated with memory

High throughput bit correction of data inside a word buffer for a p...

Updating reliability data

Estimating an error rate associated with memory

Progressive effort decoder architecture

Area efficient implementation of a product code error correcting co...

Apparatuses and methods for layer-by-layer error correction

Updating reliability data

Estimating an error rate associated with memory

Progressive effort decoder architecture

Updating reliability data with a variable node and check nodes

Estimating an error rate associated with memory

Apparatus and method using hashing for efficiently implementing an...

Channel constrained code aware interleaver

Mechanism to reduce lookup latency in a pipelined hardware implemen...

Method and system for providing cascaded trie-based network packet...

Apparatus and method of using fully configurable memory, multi-stag...

System and method for path compression optimization in a pipelined...

System and method for handling register dependency in a stack-based...

Method and system for providing cascaded trie-based network packet...

Method for increasing storage capacity in a multi-bit trie-based ha...

Method for increasing average storage capacity in a bit-mapped tree...

Instruction fetch buffer stack fold decoder for generating foldable...

Processor cache system with parity protection and method of operation

Bus interface unit having multipurpose transaction buffer

Bus interface unit having dual purpose transaction buffer

Patents Applicationslast 30 patents

ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY

HIGH THROUGHPUT BIT CORRECTION OF DATA INSIDE A WORD BUFFER FOR A P...

AREA EFFICIENT IMPLEMENTATION OF A PRODUCT CODE ERROR CORRECTING CO...

UPDATING RELIABILITY DATA

ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY

APPARATUSES AND METHODS FOR LAYER-BY-LAYER ERROR CORRECTION

PROGRESSIVE EFFORT DECODER ARCHITECTURE

ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY

UPDATING RELIABILITY DATA

ESTIMATING AN ERROR RATE ASSOCIATED WITH MEMORY

PROGRESSIVE EFFORT DECODER ARCHITECTURE

UPDATING RELIABILITY DATA

CHANNEL CONSTRAINED CODE AWARE INTERLEAVER

Method and system for providing cascaded trie-based network packet...

Apparatus and method using hashing for efficiently implementing an...

Method and system for providing cascaded trie-based network packet...

System and method for path compression optimization in a pipelined...

Mechanism to reduce lookup latency in a pipelined hardware implemen...

Apparatus and method of using fully configurable memory, multi-stag...

Method for increasing storage capacity in a multi-bit trie-based ha...

Method for increasing average storage capacity in a bit-mapped tree...

Progressive instruction folding in a processor with fast instructio...

PIPELINED NON-BLOCKING LEVEL TWO CACHE SYSTEM WITH INHERENT TRANSAC...