Nick G. Eskandari

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Handling multiple delayed write transactions simultaneously through...
- Patent number 6,442,641
- Issue date Aug 27, 2002
- Intel Corporation
- James R Bury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trigger points for performance optimization in bus-to-bus bridges
- Patent number 6,298,407
- Issue date Oct 2, 2001
- Intel Corporation
- Barry R. Davis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read latency across a bridge
- Patent number 6,260,096
- Issue date Jul 10, 2001
- Intel Corporation
- Nick G. Eskandari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient bridge architecture for handling multiple write transacti...
- Patent number 6,230,228
- Issue date May 8, 2001
- Intel Corporation
- Nick G. Eskandari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for pseudo-synchronous communication between c...
- Patent number 6,067,629
- Issue date May 23, 2000
- Intel Corporation
- Joseph Murray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for an I/O processor that integrates a PCI to PCI bridge
- Patent number 5,884,027
- Issue date Mar 16, 1999
- Intel Corporation
- Elliot Garbus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for pseudo-direct access to embedded memories...
- Patent number 5,828,825
- Issue date Oct 27, 1998
- Intel Corporation
- Nick G. Eskandari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for asynchronous, bi-directional communication...
- Patent number 5,515,530
- Issue date May 7, 1996
- Intel Corporation
- Nick G. Eskandari
- G06 - COMPUTING CALCULATING COUNTING

Nick G. Eskandari

Person

Patents Grantslast 30 patents

Handling multiple delayed write transactions simultaneously through...

Trigger points for performance optimization in bus-to-bus bridges

Read latency across a bridge

Efficient bridge architecture for handling multiple write transacti...

Apparatus and method for pseudo-synchronous communication between c...

Architecture for an I/O processor that integrates a PCI to PCI bridge

Method and apparatus for pseudo-direct access to embedded memories...

Method and apparatus for asynchronous, bi-directional communication...