Nicola Ciocchini

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamically boosting read voltage for a memory device
- Patent number 12,205,641
- Issue date Jan 21, 2025
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Grant
Read counter adjustment for delaying read disturb scans
- Patent number 12,131,788
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified read counter incrementing scheme in a memory sub-system
- Patent number 11,922,029
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial block handling in a non-volatile memory device
- Patent number 11,901,014
- Issue date Feb 13, 2024
- Micron Technology, Inc.
- Zhongguang Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods to reduce the impact of short bits in phase cha...
- Patent number 11,557,369
- Issue date Jan 17, 2023
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamically boosting read voltage for a memory device
- Patent number 11,373,705
- Issue date Jun 28, 2022
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS
- Publication number 20250014655
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES
- Publication number 20250006292
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Taylor Alu
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC ADJUSTMENT OF THRESHOLD VOLTAGE OFFSETS FOR WORDLINE GROUPS
- Publication number 20240427500
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SLOW CHARGE LOSS MONITOR FOR POWER UP PERFORMANCE BOOSTING
- Publication number 20240274202
- Publication date Aug 15, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM
- Publication number 20240160359
- Publication date May 16, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST A...
- Publication number 20240161838
- Publication date May 16, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE
- Publication number 20240145010
- Publication date May 2, 2024
- Micron Technology, Inc.
- Zhongguang Xu
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE READ DISTURB SCAN
- Publication number 20240126448
- Publication date Apr 18, 2024
- Micron Technology, Inc.
- Animesh R. Chowdhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTIO...
- Publication number 20240071547
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Guang Hu
- G11 - INFORMATION STORAGE
Information Patent Application
READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS
- Publication number 20240071522
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
PARTIAL BLOCK READ VOLTAGE OFFSET
- Publication number 20240071506
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Zhongguang XU
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM
- Publication number 20230393756
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE
- Publication number 20230360704
- Publication date Nov 9, 2023
- Micron Technology, Inc.
- Zhongguang Xu
- G11 - INFORMATION STORAGE
Information Patent Application
BINARY NEURAL NETWORK IN MEMORY
- Publication number 20220366224
- Publication date Nov 17, 2022
- Micron Technology, Inc.
- Dmitry Vengertsev
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods to Reduce the Impact of Short Bits in Phase Cha...
- Publication number 20220319629
- Publication date Oct 6, 2022
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMICALLY BOOSTING READ VOLTAGE FOR A MEMORY DEVICE
- Publication number 20220301623
- Publication date Sep 22, 2022
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMICALLY BOOSTING READ VOLTAGE FOR A MEMORY DEVICE
- Publication number 20220165333
- Publication date May 26, 2022
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE

Nicola Ciocchini

Person

Patents Grantslast 30 patents

Dynamically boosting read voltage for a memory device

Read counter adjustment for delaying read disturb scans

Modified read counter incrementing scheme in a memory sub-system

Partial block handling in a non-volatile memory device

Systems and methods to reduce the impact of short bits in phase cha...

Dynamically boosting read voltage for a memory device

Patents Applicationslast 30 patents

READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS

STABLE STATE ERROR-HANDLING BIN SELECTION IN MEMORY DEVICES

DYNAMIC ADJUSTMENT OF THRESHOLD VOLTAGE OFFSETS FOR WORDLINE GROUPS

SLOW CHARGE LOSS MONITOR FOR POWER UP PERFORMANCE BOOSTING

MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM

MEDIA MANAGEMENT SCANNING WITH UNIFIED CRITERIA TO ALLEVIATE FAST A...

PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE

ADAPTIVE READ DISTURB SCAN

BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTIO...

READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS

PARTIAL BLOCK READ VOLTAGE OFFSET

MODIFIED READ COUNTER INCREMENTING SCHEME IN A MEMORY SUB-SYSTEM

PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE

BINARY NEURAL NETWORK IN MEMORY

Systems and Methods to Reduce the Impact of Short Bits in Phase Cha...

DYNAMICALLY BOOSTING READ VOLTAGE FOR A MEMORY DEVICE

DYNAMICALLY BOOSTING READ VOLTAGE FOR A MEMORY DEVICE