Nicola Del Gatto

Person

Torre Del Greco, IT

People

Patents Grantslast 30 patents

Information Patent Grant
Controller to alter systems based on metrics and telemetry
- Patent number 12,124,729
- Issue date Oct 22, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-level refresh management
- Patent number 12,105,971
- Issue date Oct 1, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for managing raid information
- Patent number 12,093,566
- Issue date Sep 17, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read data path
- Patent number 11,989,088
- Issue date May 21, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache architectures with address delay registers for memory devices
- Patent number 11,954,035
- Issue date Apr 9, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write command execution for data protection and recovery schemes
- Patent number 11,934,270
- Issue date Mar 19, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managed memory systems with multiple priority queues
- Patent number 11,914,893
- Issue date Feb 27, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interrupt mode or polling mode for memory devices
- Patent number 11,886,749
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Federica Cresci
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cleaning memory blocks using multiple types of write operations
- Patent number 11,763,887
- Issue date Sep 19, 2023
- Micron Technology, Inc.
- Nicola Del Gatto
- G11 - INFORMATION STORAGE
Information Patent Grant
Low latency storage based on data size
- Patent number 11,720,284
- Issue date Aug 8, 2023
- Micron Technology, Inc.
- Federica Cresci
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interrupt mode or polling mode for memory devices
- Patent number 11,561,733
- Issue date Jan 24, 2023
- Micron Technology, Inc.
- Federica Cresci
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache architectures with address delay registers for memory devices
- Patent number 11,481,330
- Issue date Oct 25, 2022
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cleaning memory blocks using multiple types of write operations
- Patent number 11,468,948
- Issue date Oct 11, 2022
- Micron Technology, Inc.
- Nicola Del Gatto
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for distributing a test signal applied to a pad of an elect...
- Patent number 7,750,656
- Issue date Jul 6, 2010
- STMicroelectronics S.r.l.
- Nicola Del Gatto
- G01 - MEASURING TESTING
Information Patent Grant
Voltage regulator for the programming circuit of a memory cell
- Patent number 7,706,193
- Issue date Apr 27, 2010
- Davide Cascone
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device employing three-level cells and related methods of ma...
- Patent number 7,596,023
- Issue date Sep 29, 2009
- Alessandro Magnavacca
- G11 - INFORMATION STORAGE
Information Patent Grant
Reading circuit for semiconductor memory
- Patent number 7,508,717
- Issue date Mar 24, 2009
- Nicola Del Gatto
- G11 - INFORMATION STORAGE
Information Patent Grant
Regulator of a digital-to-analog converter and related converter
- Patent number 7,400,281
- Issue date Jul 15, 2008
- STMicroelectronics, SRL
- Roberto Versari
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for configuring a voltage regulator
- Patent number 7,388,793
- Issue date Jun 17, 2008
- STMicroelectronics S.r.l.
- Davide Cascone
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with a ramp-like voltage biasing structure based on a...
- Patent number 7,359,246
- Issue date Apr 15, 2008
- STMicroelectronics S.r.l.
- Marco Sforzin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 7,352,645
- Issue date Apr 1, 2008
- STMicroelectronics S.r.l.
- Marco Sforzin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of operating the same with high rejection...
- Patent number 7,324,379
- Issue date Jan 29, 2008
- STMicroelectronics S.r.l.
- Nicola Del Gatto
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming method of multilevel memories and corresponding circuit
- Patent number 7,317,637
- Issue date Jan 8, 2008
- STMicroelectronics S.r.l.
- Emanuele Confalonieri
- G11 - INFORMATION STORAGE
Information Patent Grant
Control of voltages during erase and re-program operations of memor...
- Patent number 7,289,368
- Issue date Oct 30, 2007
- STMicroelectronics S.r.l.
- Nicola Del Gatto
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming method for non volatile multilevel memory cells and cor...
- Patent number 6,934,185
- Issue date Aug 23, 2005
- STMicroelectronics S.r.l.
- Emanuele Confalonieri
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage regulator with very quick response
- Patent number 6,909,264
- Issue date Jun 21, 2005
- STMicroelectronics S.r.l.
- Nicola Del Gatto
- G05 - CONTROLLING REGULATING
Information Patent Grant
Circuit for biasing an input node of a sense amplifier with a pre-c...
- Patent number 6,856,547
- Issue date Feb 15, 2005
- STMicroelectronics S.r.l.
- Carla Poidomani
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DUAL-LEVEL REFRESH MANAGEMENT
- Publication number 20250004656
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER FOR MANAGING RAID INFORMATION
- Publication number 20240427526
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read Data Path
- Publication number 20240427660
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGED MEMORY SYSTEMS WITH MULTIPLE PRIORITY QUEUES
- Publication number 20240272831
- Publication date Aug 15, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Read Data Path
- Publication number 20240070015
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER CACHE ARCHITETURE
- Publication number 20240004791
- Publication date Jan 4, 2024
- Micron Technology, Inc.
- Emanuele Confalonieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE BYPASS
- Publication number 20230418756
- Publication date Dec 28, 2023
- Micron Technology, Inc.
- Emanuele Confalonieri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE COMMAND EXECUTION FOR DATA PROTECTION AND RECOVERY SCHEMES
- Publication number 20230393940
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER FOR MANAGING RAID INFORMATION
- Publication number 20230280940
- Publication date Sep 7, 2023
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERRUPT MODE OR POLLING MODE FOR MEMORY DEVICES
- Publication number 20230205462
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Federica Cresci
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-LEVEL REFRESH MANAGEMENT
- Publication number 20230195337
- Publication date Jun 22, 2023
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE ARCHITECTURES FOR MEMORY DEVICES
- Publication number 20230100015
- Publication date Mar 30, 2023
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLEANING MEMORY BLOCKS USING MULTIPLE TYPES OF WRITE OPERATIONS
- Publication number 20230070436
- Publication date Mar 9, 2023
- Micron Technology, Inc.
- Nicola Del Gatto
- G11 - INFORMATION STORAGE
Information Patent Application
LOW LATENCY STORAGE BASED ON DATA SIZE
- Publication number 20220350533
- Publication date Nov 3, 2022
- Micron Technology, Inc.
- Federica Cresci
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER FOR MANAGING METRICS AND TELEMETRY
- Publication number 20220326874
- Publication date Oct 13, 2022
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVENT MANAGEMENT FOR MEMORY DEVICES
- Publication number 20220253242
- Publication date Aug 11, 2022
- Micron Technology, Inc.
- Federica Cresci
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLEANING MEMORY BLOCKS USING MULTIPLE TYPES OF WRITE OPERATIONS
- Publication number 20220230683
- Publication date Jul 21, 2022
- Micron Technology, Inc.
- Nicola Del Gatto
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGED MEMORY SYSTEMS WITH MULTIPLE PRIORITY QUEUES
- Publication number 20220155997
- Publication date May 19, 2022
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE BUFFER PARTITIONING
- Publication number 20220057958
- Publication date Feb 24, 2022
- Micron Technology, Inc.
- Massimiliano Patriarca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE ARCHITECTURES FOR MEMORY DEVICES
- Publication number 20210382823
- Publication date Dec 9, 2021
- Micron Technology, Inc.
- Nicola Del Gatto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE REGULATOR FOR THE PROGRAMMING CIRCUIT OF A MEMORY CELL
- Publication number 20080094906
- Publication date Apr 24, 2008
- STMicroelectronics S.r. I.
- Davide Cascone
- G11 - INFORMATION STORAGE
Information Patent Application
READING CIRCUIT FOR SEMICONDUCTOR MEMORY
- Publication number 20070258301
- Publication date Nov 8, 2007
- STMicroelectronics S.r. I.
- Nicola Del Gatto
- G11 - INFORMATION STORAGE
Information Patent Application
REGULATOR OF A DIGITAL-TO-ANALOG CONVERTER AND RELATED CONVERTER
- Publication number 20070210949
- Publication date Sep 13, 2007
- STMicroelectronics S.r.l.
- Roberto Versari
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory device with a ramp-like voltage biasing structure based on a...
- Publication number 20060198187
- Publication date Sep 7, 2006
- STMicroelectronics S.r.l.
- Marco Sforzin
- G11 - INFORMATION STORAGE
Information Patent Application
Control of voltages during erase and re-program operations of memor...
- Publication number 20060171213
- Publication date Aug 3, 2006
- STMicroelectronics S.r.l.
- Nicola Del Gatto
- G11 - INFORMATION STORAGE
Information Patent Application
Method for configuring a voltage regulator
- Publication number 20060133148
- Publication date Jun 22, 2006
- STMicroelectronics S.r.l.
- Davide Cascone
- G11 - INFORMATION STORAGE
Information Patent Application
Programming method of multilevel memories and corresponding circuit
- Publication number 20060120161
- Publication date Jun 8, 2006
- STMicroelectronics S.r. I.
- Emanuele Confalonieri
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device
- Publication number 20060083078
- Publication date Apr 20, 2006
- STMicroelectronics S.r. I.
- Marco Sforzin
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit for biasing an input node of a sense amplifier with a pre-c...
- Publication number 20040125670
- Publication date Jul 1, 2004
- STMicroelectronics S.r.l.
- Carla Poidomani
- G11 - INFORMATION STORAGE
Information Patent Application
Voltage regulator with very quick response
- Publication number 20040075422
- Publication date Apr 22, 2004
- STMicroelectronics S.r.l.
- Nicola Del Gatto
- G05 - CONTROLLING REGULATING

Nicola Del Gatto

Person

Patents Grantslast 30 patents

Controller to alter systems based on metrics and telemetry

Dual-level refresh management

Memory controller for managing raid information

Read data path

Cache architectures with address delay registers for memory devices

Write command execution for data protection and recovery schemes

Managed memory systems with multiple priority queues

Interrupt mode or polling mode for memory devices

Cleaning memory blocks using multiple types of write operations

Low latency storage based on data size

Interrupt mode or polling mode for memory devices

Cache architectures with address delay registers for memory devices

Cleaning memory blocks using multiple types of write operations

Circuit for distributing a test signal applied to a pad of an elect...

Voltage regulator for the programming circuit of a memory cell

Memory device employing three-level cells and related methods of ma...

Reading circuit for semiconductor memory

Regulator of a digital-to-analog converter and related converter

Method for configuring a voltage regulator

Memory device with a ramp-like voltage biasing structure based on a...

Memory device

Memory device and method of operating the same with high rejection...

Programming method of multilevel memories and corresponding circuit

Control of voltages during erase and re-program operations of memor...

Programming method for non volatile multilevel memory cells and cor...

Voltage regulator with very quick response

Circuit for biasing an input node of a sense amplifier with a pre-c...

Patents Applicationslast 30 patents

DUAL-LEVEL REFRESH MANAGEMENT

MEMORY CONTROLLER FOR MANAGING RAID INFORMATION

Read Data Path

MANAGED MEMORY SYSTEMS WITH MULTIPLE PRIORITY QUEUES

Read Data Path

CONTROLLER CACHE ARCHITETURE

CACHE BYPASS

WRITE COMMAND EXECUTION FOR DATA PROTECTION AND RECOVERY SCHEMES

MEMORY CONTROLLER FOR MANAGING RAID INFORMATION

INTERRUPT MODE OR POLLING MODE FOR MEMORY DEVICES

DUAL-LEVEL REFRESH MANAGEMENT

CACHE ARCHITECTURES FOR MEMORY DEVICES

CLEANING MEMORY BLOCKS USING MULTIPLE TYPES OF WRITE OPERATIONS

LOW LATENCY STORAGE BASED ON DATA SIZE

CONTROLLER FOR MANAGING METRICS AND TELEMETRY

EVENT MANAGEMENT FOR MEMORY DEVICES

CLEANING MEMORY BLOCKS USING MULTIPLE TYPES OF WRITE OPERATIONS

MANAGED MEMORY SYSTEMS WITH MULTIPLE PRIORITY QUEUES

ADAPTIVE BUFFER PARTITIONING

CACHE ARCHITECTURES FOR MEMORY DEVICES

VOLTAGE REGULATOR FOR THE PROGRAMMING CIRCUIT OF A MEMORY CELL

READING CIRCUIT FOR SEMICONDUCTOR MEMORY

REGULATOR OF A DIGITAL-TO-ANALOG CONVERTER AND RELATED CONVERTER

Memory device with a ramp-like voltage biasing structure based on a...

Control of voltages during erase and re-program operations of memor...

Method for configuring a voltage regulator

Programming method of multilevel memories and corresponding circuit

Memory device

Circuit for biasing an input node of a sense amplifier with a pre-c...

Voltage regulator with very quick response