Nicolas Breil

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Formation of metal vias on metal lines
- Patent number 12,113,020
- Issue date Oct 8, 2024
- Applied Materials, Inc.
- Ryan Scott Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide films through selective deposition
- Patent number 11,978,635
- Issue date May 7, 2024
- Applied Materials, Inc.
- Swaminathan Srinivasan
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Methods of forming doped silicide power devices
- Patent number 11,605,741
- Issue date Mar 14, 2023
- Applied Materials, Inc.
- Joshua S. Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Annealing processes for memory devices
- Patent number 11,362,275
- Issue date Jun 14, 2022
- Applied Materials, Inc.
- Nicolas Louis Gabriel Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor and method of forming same
- Patent number 11,088,280
- Issue date Aug 10, 2021
- International Business Machines Corporation
- Veeraraghavan S. Basker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Soi FinFET fins with recessed fins and epitaxy in source drain region
- Patent number 11,069,809
- Issue date Jul 20, 2021
- GLOBALFOUNDRIES U.S. INC.
- Alexander Reznicek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide films through selective deposition
- Patent number 10,950,450
- Issue date Mar 16, 2021
- Applied Materials, Inc.
- Swaminathan Srinivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for detecting voids and an inspection system
- Patent number 10,922,809
- Issue date Feb 16, 2021
- Applied Materials, Inc.
- Dror Shemesh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Contacts to semiconductor substrate and methods of forming same
- Patent number 10,707,167
- Issue date Jul 7, 2020
- GLOBALFOUNDRIES Inc.
- Emre Alptekin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide films through selective deposition
- Patent number 10,607,841
- Issue date Mar 31, 2020
- Applied Materials, Inc.
- Swaminathan Srinivasan
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Modified tungsten silicon
- Patent number 10,096,609
- Issue date Oct 9, 2018
- GLOBALFOUNDRIES Inc.
- Nicolas L. Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon germanium fins on insulator formed by lateral recrystalliza...
- Patent number 10,068,920
- Issue date Sep 4, 2018
- GLOBALFOUNDRIES Inc.
- Alexander Reznicek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voidless contact metal structures
- Patent number 9,997,407
- Issue date Jun 12, 2018
- International Business Machines Corporation
- Veeraraghavan S. Basker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor and method of forming same
- Patent number 9,911,849
- Issue date Mar 6, 2018
- International Business Machines Corporation
- Veeraraghavan S. Basker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI FinFET fins with recessed fins and epitaxy in source drain region
- Patent number 9,905,692
- Issue date Feb 27, 2018
- GLOBALFOUNDRIES Inc.
- Alexander Reznicek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contacts to semiconductor substrate and methods of forming same
- Patent number 9,865,546
- Issue date Jan 9, 2018
- GLOBALFOUNDRIES Inc.
- Emre Alptekin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple step thin film deposition method for high conformality
- Patent number 9,859,403
- Issue date Jan 2, 2018
- GLOBALFOUNDRIES Inc.
- Nicolas L. Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voidless contact metal structures
- Patent number 9,859,216
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Veeraraghavan S. Basker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DT capacitor with silicide outer electrode and/or compressive stres...
- Patent number 9,653,535
- Issue date May 16, 2017
- International Business Machines Corporation
- Nicolas L. Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET source-drain merged by silicide-based material
- Patent number 9,595,524
- Issue date Mar 14, 2017
- GLOBALFOUNDRIES Inc.
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET source-drain merged by silicide-based material
- Patent number 9,543,167
- Issue date Jan 10, 2017
- GLOBALFOUNDRIES Inc.
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DT capacitor with silicide outer electrode and/or compressive stres...
- Patent number 9,496,329
- Issue date Nov 15, 2016
- International Business Machines Corporation
- Nicolas L. Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal semiconductor alloy contact resistance improvement
- Patent number 9,472,406
- Issue date Oct 18, 2016
- International Business Machines Corporation
- Emre Alptekin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal semiconductor alloy contact resistance improvement
- Patent number 9,449,827
- Issue date Sep 20, 2016
- International Business Machines Corporation
- Emre Alptekin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Voidless contact metal structures
- Patent number 9,449,921
- Issue date Sep 20, 2016
- International Business Machines Corporation
- Veeraraghavan S. Basker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diffusion-controlled semiconductor contact creation
- Patent number 9,443,772
- Issue date Sep 13, 2016
- GLOBALFOUNDRIES Inc.
- Emre Alptekin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Asymmetric field effect transistor cap layer
- Patent number 9,431,534
- Issue date Aug 30, 2016
- GLOBALFOUNDRIES Inc.
- Nicolas L. Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stable nickel silicide formation with fluorine incorporation and re...
- Patent number 9,379,207
- Issue date Jun 28, 2016
- GLOBALFOUNDRIES, INC.
- Nicolas L. Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxide mediated epitaxial nickel disilicide alloy contact formation
- Patent number 9,379,012
- Issue date Jun 28, 2016
- GLOBALFOUNDRIES Inc.
- Emre Alptekin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for laser heating and ion implantation
- Patent number 9,373,512
- Issue date Jun 21, 2016
- GLOBALFOUNDRIES, INC.
- Nicolas Breil
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHODS OF REDUCING BACKSIDE CONTACT RESISTANCE
- Publication number 20240332388
- Publication date Oct 3, 2024
- Applied Materials, Inc.
- Byeong Chan Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods For Forming Gate Structures
- Publication number 20240304671
- Publication date Sep 12, 2024
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT RESISTANCE REDUCTION BY INTEGRATION OF MOLYBDENUM WITH TITA...
- Publication number 20240234209
- Publication date Jul 11, 2024
- Applied Materials, Inc.
- Avgerinos V. Gelatos
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT LAYER FORMATION WITH MICROWAVE ANNEALING FOR NMOS DEVICES
- Publication number 20240203742
- Publication date Jun 20, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAVITY SHAPING AND SELECTIVE METAL SILICIDE FORMATION FOR CMOS DEVICES
- Publication number 20240203741
- Publication date Jun 20, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SACRIFICIAL SOURCE/DRAIN FOR METALLIC SOURCE/DRAIN HORIZONTAL GATE...
- Publication number 20240128355
- Publication date Apr 18, 2024
- Applied Materials, Inc.
- Nicolas Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIDDLE OF LINE DIELECTRIC LAYER ENGINEERING FOR VIA VOID PREVENTION
- Publication number 20240105505
- Publication date Mar 28, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MIDDLE OF LINE DIELECTRIC LAYER ENGINEERING FOR VIA VOID PREVENTION
- Publication number 20240105509
- Publication date Mar 28, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OXIDATION BARRIERS WITH CVD SOAK PROCESSES
- Publication number 20240018647
- Publication date Jan 18, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
SELECTIVE CAPPING OF CONTACT LAYER FOR CMOS DEVICES
- Publication number 20240014076
- Publication date Jan 11, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT FORMATION PROCESS FOR CMOS DEVICES
- Publication number 20240014075
- Publication date Jan 11, 2024
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT FORMATION PROCESS FOR CMOS DEVICES
- Publication number 20230377997
- Publication date Nov 23, 2023
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW TEMPERATURE N-TYPE CONTACT EPI FORMATION
- Publication number 20230307506
- Publication date Sep 28, 2023
- Applied Materials, Inc.
- Nicolas Breil
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
SELECTIVE SILICIDE DEPOSITION FOR 3-D DRAM
- Publication number 20230044391
- Publication date Feb 9, 2023
- Applied Materials, Inc.
- Nicolas Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VOID-FREE CONTACT TRENCH FILL IN GATE-ALL-AROUND FET ARCHTECTURE
- Publication number 20220384258
- Publication date Dec 1, 2022
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHODS FOR DRAM CONTACT FORMATION
- Publication number 20220336469
- Publication date Oct 20, 2022
- Applied Materials, Inc.
- Nicolas Louis BREIL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF METAL VIAS ON METAL LINES
- Publication number 20220270979
- Publication date Aug 25, 2022
- Applied Materials, Inc.
- Ryan Scott Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING DOPED SILICIDE POWER DEVICES
- Publication number 20220165574
- Publication date May 26, 2022
- Applied Materials, Inc.
- Joshua S. Holt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicide Films Through Selective Deposition
- Publication number 20210202256
- Publication date Jul 1, 2021
- Applied Materials, Inc.
- Swaminathan Srinivasan
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
ANNEALING PROCESSES FOR MEMORY DEVICES
- Publication number 20200357993
- Publication date Nov 12, 2020
- Applied Materials, Inc.
- Nicolas Louis Gabriel Breil
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANNEALING PROCESSES TO STABILIZE NICKEL-CONTAINING FILMS
- Publication number 20200335329
- Publication date Oct 22, 2020
- Applied Materials, Inc.
- Jeffery W. Anthis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICIDE FILMS THROUGH SELECTIVE DEPOSITION
- Publication number 20200227265
- Publication date Jul 16, 2020
- Applied Materials, Inc.
- Swaminathan Srinivasan
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
METHODS OF FORMING NICKEL-CONTAINING FILMS
- Publication number 20200106012
- Publication date Apr 2, 2020
- Applied Materials, Inc.
- Hung Nguyen
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
PHYSICAL VAPOR DEPOSITION OF DOPED TRANSITION METAL OXIDE AND POST-...
- Publication number 20200044152
- Publication date Feb 6, 2020
- Applied Materials, Inc.
- MINRUI YU
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Silicide Films Through Selective Deposition
- Publication number 20190189453
- Publication date Jun 20, 2019
- Applied Materials, Inc.
- Swaminathan Srinivasan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR DETECTING VOIDS AND AN INSPECTION SYSTEM
- Publication number 20190043183
- Publication date Feb 7, 2019
- Applied Materials, Inc.
- Dror Shemesh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION
- Publication number 20180175197
- Publication date Jun 21, 2018
- GLOBALFOUNDRIES INC.
- Alexander Reznicek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR AND METHOD OF FORMING SAME
- Publication number 20180097112
- Publication date Apr 5, 2018
- International Business Machines Corporation
- Veeraraghavan S. Basker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME
- Publication number 20180090447
- Publication date Mar 29, 2018
- GLOBALFOUNDRIES INC.
- Emre Alptekin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE STEP THIN FILM DEPOSITION METHOD FOR HIGH CONFORMALITY
- Publication number 20180026118
- Publication date Jan 25, 2018
- GLOBALFOUNDRIES INC.
- Nicolas L. Breil
- H01 - BASIC ELECTRIC ELEMENTS

Nicolas Breil

Person

Patents Grantslast 30 patents

Formation of metal vias on metal lines

Silicide films through selective deposition

Methods of forming doped silicide power devices

Annealing processes for memory devices

Transistor and method of forming same

Soi FinFET fins with recessed fins and epitaxy in source drain region

Silicide films through selective deposition

Method for detecting voids and an inspection system

Contacts to semiconductor substrate and methods of forming same

Silicide films through selective deposition

Modified tungsten silicon

Silicon germanium fins on insulator formed by lateral recrystalliza...

Voidless contact metal structures

Transistor and method of forming same

SOI FinFET fins with recessed fins and epitaxy in source drain region

Contacts to semiconductor substrate and methods of forming same

Multiple step thin film deposition method for high conformality

Voidless contact metal structures

DT capacitor with silicide outer electrode and/or compressive stres...

FinFET source-drain merged by silicide-based material

FinFET source-drain merged by silicide-based material

DT capacitor with silicide outer electrode and/or compressive stres...

Metal semiconductor alloy contact resistance improvement

Metal semiconductor alloy contact resistance improvement

Voidless contact metal structures

Diffusion-controlled semiconductor contact creation

Asymmetric field effect transistor cap layer

Stable nickel silicide formation with fluorine incorporation and re...

Oxide mediated epitaxial nickel disilicide alloy contact formation

Apparatus and method for laser heating and ion implantation

Patents Applicationslast 30 patents

METHODS OF REDUCING BACKSIDE CONTACT RESISTANCE

Methods For Forming Gate Structures

CONTACT RESISTANCE REDUCTION BY INTEGRATION OF MOLYBDENUM WITH TITA...

CONTACT LAYER FORMATION WITH MICROWAVE ANNEALING FOR NMOS DEVICES

CAVITY SHAPING AND SELECTIVE METAL SILICIDE FORMATION FOR CMOS DEVICES

SACRIFICIAL SOURCE/DRAIN FOR METALLIC SOURCE/DRAIN HORIZONTAL GATE...

MIDDLE OF LINE DIELECTRIC LAYER ENGINEERING FOR VIA VOID PREVENTION

MIDDLE OF LINE DIELECTRIC LAYER ENGINEERING FOR VIA VOID PREVENTION

OXIDATION BARRIERS WITH CVD SOAK PROCESSES

SELECTIVE CAPPING OF CONTACT LAYER FOR CMOS DEVICES

CONTACT FORMATION PROCESS FOR CMOS DEVICES

CONTACT FORMATION PROCESS FOR CMOS DEVICES

LOW TEMPERATURE N-TYPE CONTACT EPI FORMATION

SELECTIVE SILICIDE DEPOSITION FOR 3-D DRAM

VOID-FREE CONTACT TRENCH FILL IN GATE-ALL-AROUND FET ARCHTECTURE

SYSTEM AND METHODS FOR DRAM CONTACT FORMATION

FORMATION OF METAL VIAS ON METAL LINES

METHODS OF FORMING DOPED SILICIDE POWER DEVICES

Silicide Films Through Selective Deposition

ANNEALING PROCESSES FOR MEMORY DEVICES

ANNEALING PROCESSES TO STABILIZE NICKEL-CONTAINING FILMS

SILICIDE FILMS THROUGH SELECTIVE DEPOSITION

METHODS OF FORMING NICKEL-CONTAINING FILMS

PHYSICAL VAPOR DEPOSITION OF DOPED TRANSITION METAL OXIDE AND POST-...

Silicide Films Through Selective Deposition

METHOD FOR DETECTING VOIDS AND AN INSPECTION SYSTEM

SOI FINFET FINS WITH RECESSED FINS AND EPITAXY IN SOURCE DRAIN REGION

TRANSISTOR AND METHOD OF FORMING SAME

CONTACTS TO SEMICONDUCTOR SUBSTRATE AND METHODS OF FORMING SAME

MULTIPLE STEP THIN FILM DEPOSITION METHOD FOR HIGH CONFORMALITY