Nigel Chan

Person

Dresden, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor structure including sectioned well region
- Patent number 12,046,603
- Issue date Jul 23, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Eight-transistor static random access memory cell
- Patent number 11,488,967
- Issue date Nov 1, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Jörg D. Schmid
- G11 - INFORMATION STORAGE
Information Patent Grant
Extended-drain field-effect transistors including a floating gate
- Patent number 11,127,860
- Issue date Sep 21, 2021
- GLOBALFOUNDRIES U.S. INC.
- Ming-Cheng Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC product with a novel bit cell design and a memory array comprisi...
- Patent number 10,923,482
- Issue date Feb 16, 2021
- GLOBALFOUNDRIES U.S. INC.
- Germain Bossu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Well contact cell with doped tap region separated from active regio...
- Patent number 10,909,298
- Issue date Feb 2, 2021
- GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KG
- Nigel Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-voltage transistor device with thick gate insulation layers
- Patent number 10,811,433
- Issue date Oct 20, 2020
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Deep fence isolation for logic cells
- Patent number 10,593,674
- Issue date Mar 17, 2020
- GLOBALFOUNDRIES Inc.
- Ming-Cheng Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-depth STI cavity extension and method of production thereof
- Patent number 10,559,490
- Issue date Feb 11, 2020
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET SRAM layout and method of making the same
- Patent number 10,504,906
- Issue date Dec 10, 2019
- GLOBALFOUNDRIES Inc.
- Ming-Cheng Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-voltage transistor device with thick gate insulation layers
- Patent number 10,418,380
- Issue date Sep 17, 2019
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices including self-aligned active regions for pla...
- Patent number 10,396,084
- Issue date Aug 27, 2019
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High voltage transistor using buried insulating layer as gate diele...
- Patent number 10,319,827
- Issue date Jun 11, 2019
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alignment key design rule check for correct placement of abutting c...
- Patent number 10,311,201
- Issue date Jun 4, 2019
- GLOBALFOUNDRIES Inc.
- Nigel Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SOI-based floating gate memory cell
- Patent number 10,177,163
- Issue date Jan 8, 2019
- GLOBALFOUNDRIES Inc.
- Nigel Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming integrated circuits that include a dummy gate s...
- Patent number 10,157,996
- Issue date Dec 18, 2018
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with back-gate switching
- Patent number 10,079,605
- Issue date Sep 18, 2018
- GLOBALFOUNDRIES Inc.
- Michael Otto
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor structure including a first transistor at a semicondu...
- Patent number 9,847,347
- Issue date Dec 19, 2017
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit including a dummy gate structure and method for...
- Patent number 9,793,372
- Issue date Oct 17, 2017
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inline monitoring of transistor-to-transistor critical dimension
- Patent number 9,768,084
- Issue date Sep 19, 2017
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure with back-gate switching
- Patent number 9,762,245
- Issue date Sep 12, 2017
- GLOBALFOUNDRIES Inc.
- Michael Otto
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Process monitoring for gate cut mask
- Patent number 9,685,336
- Issue date Jun 20, 2017
- GLOBALFOUNDRIES Inc.
- Nigel Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer with SOI structure having a buried insulating multilayer stru...
- Patent number 9,590,118
- Issue date Mar 7, 2017
- GLOBALFOUNDRIES Inc.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device comprising a plurality of FDSOI static random-access memory...
- Patent number 9,490,007
- Issue date Nov 8, 2016
- GLOBALFOUNDRIES Inc.
- Nigel Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell assembly including an avoid disturb cell
- Patent number 8,953,388
- Issue date Feb 10, 2015
- GLOBALFOUNDRIES, INC.
- Michael Otto
- G11 - INFORMATION STORAGE
Information Patent Grant
Device including an array of memory cells and well contact areas, a...
- Patent number 8,921,898
- Issue date Dec 30, 2014
- GLOBALFOUNDRIES Inc.
- Nigel Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device comprising a plurality of static random access memory cells...
- Patent number 8,817,528
- Issue date Aug 26, 2014
- GLOBALFOUNDRIES Inc.
- Michael Otto
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid read scheme for multi-level data
- Patent number 8,509,007
- Issue date Aug 13, 2013
- Infineon Technologies AG
- Thomas Nirschl
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with predictive programming
- Patent number 8,243,520
- Issue date Aug 14, 2012
- Infineon Technologies AG
- Nigel Chan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
IC STRUCTURE FOR CONNECTED CAPACITANCES AND METHOD OF FORMING SAME
- Publication number 20240371879
- Publication date Nov 7, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Germain Bossu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
- Publication number 20240282776
- Publication date Aug 22, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
- Publication number 20230163134
- Publication date May 25, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL
- Publication number 20220310629
- Publication date Sep 29, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Jörg D. Schmid
- G11 - INFORMATION STORAGE
Information Patent Application
EXTENDED-DRAIN FIELD-EFFECT TRANSISTORS INCLUDING A FLOATING GATE
- Publication number 20210083095
- Publication date Mar 18, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Ming-Cheng Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC PRODUCT WITH A NOVEL BIT CELL DESIGN AND A MEMORY ARRAY COMPRISI...
- Publication number 20200343248
- Publication date Oct 29, 2020
- GLOBALFOUNDRIES INC.
- Germain Bossu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEEP FENCE ISOLATION FOR LOGIC CELLS
- Publication number 20200083223
- Publication date Mar 12, 2020
- GLOBALFOUNDRIES INC.
- Ming-Cheng CHANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL-DEPTH STI CAVITY EXTENSION AND METHOD OF PRODUCTION THEREOF
- Publication number 20200066573
- Publication date Feb 27, 2020
- GLOBALFOUNDRIES INC.
- Elliot John SMITH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-VOLTAGE TRANSISTOR DEVICE WITH THICK GATE INSULATION LAYERS
- Publication number 20190319048
- Publication date Oct 17, 2019
- GLOBALFOUNDRIES INC.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING FDSOI TRANSISTORS WITH COMPACT GROUN...
- Publication number 20190312038
- Publication date Oct 10, 2019
- GLOBALFOUNDRIES INC.
- Nigel Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET SRAM LAYOUT AND METHOD OF MAKING THE SAME
- Publication number 20190172832
- Publication date Jun 6, 2019
- GLOBALFOUNDRIES INC.
- Ming-Cheng Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ALIGNMENT KEY DESIGN RULE CHECK FOR CORRECT PLACEMENT OF ABUTTING C...
- Publication number 20190042689
- Publication date Feb 7, 2019
- GLOBALFOUNDRIES INC.
- Nigel Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-VOLTAGE TRANSISTOR DEVICE WITH THICK GATE INSULATION LAYERS
- Publication number 20190035815
- Publication date Jan 31, 2019
- GLOBALFOUNDRIES INC.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH VOLTAGE TRANSISTOR USING BURIED INSULATING LAYER AS GATE DIELE...
- Publication number 20190019876
- Publication date Jan 17, 2019
- GLOBALFOUNDRIES INC.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE WITH BACK-GATE SWITCHING
- Publication number 20170359070
- Publication date Dec 14, 2017
- GLOBALFOUNDRIES INC.
- Michael OTTO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS FOR FORMING INTEGRATED CIRCUITS THAT INCLUDE A DUMMY GATE S...
- Publication number 20170345914
- Publication date Nov 30, 2017
- GLOBALFOUNDRIES INC.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INLINE MONITORING OF TRANSISTOR-TO-TRANSISTOR CRITICAL DIMENSION
- Publication number 20170271220
- Publication date Sep 21, 2017
- GLOBALFOUNDRIES INC.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER WITH SOI STRUCTURE HAVING A BURIED INSULATING MULTILAYER STRU...
- Publication number 20170077314
- Publication date Mar 16, 2017
- GLOBALFOUNDRIES INC.
- Elliot John Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE COMPRISING A PLURALITY OF FDSOI STATIC RANDOM-ACCESS MEMORY...
- Publication number 20160343428
- Publication date Nov 24, 2016
- GLOBALFOUNDRIES INC.
- Nigel Chan
- G11 - INFORMATION STORAGE
Information Patent Application
DEVICE INCLUDING AN ARRAY OF MEMORY CELLS AND WELL CONTACT AREAS, A...
- Publication number 20140367794
- Publication date Dec 18, 2014
- Nigel Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE COMPRISING A PLURALITY OF STATIC RANDOM ACCESS MEMORY CELLS...
- Publication number 20140050017
- Publication date Feb 20, 2014
- GLOBALFOUNDRIES INC.
- Michael Otto
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL ASSEMBLY INCLUDING AN AVOID DISTURB CELL
- Publication number 20140050033
- Publication date Feb 20, 2014
- GLOBALFOUNDRIES INC.
- Michael Otto
- G11 - INFORMATION STORAGE
Information Patent Application
Hybrid Read Scheme for Multi-Level Data
- Publication number 20120170386
- Publication date Jul 5, 2012
- INFINEON TECHNOLOGIES AG
- Thomas Nirschl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING
- Publication number 20110103150
- Publication date May 5, 2011
- INFINEON TECHNOLOGIES AG
- Nigel Chan
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Semiconductor structure including sectioned well region

Eight-transistor static random access memory cell

Extended-drain field-effect transistors including a floating gate

IC product with a novel bit cell design and a memory array comprisi...

Well contact cell with doped tap region separated from active regio...

High-voltage transistor device with thick gate insulation layers

Deep fence isolation for logic cells

Dual-depth STI cavity extension and method of production thereof

FinFET SRAM layout and method of making the same

High-voltage transistor device with thick gate insulation layers

Semiconductor devices including self-aligned active regions for pla...

High voltage transistor using buried insulating layer as gate diele...

Alignment key design rule check for correct placement of abutting c...

SOI-based floating gate memory cell

Methods for forming integrated circuits that include a dummy gate s...

Semiconductor structure with back-gate switching

Semiconductor structure including a first transistor at a semicondu...

Integrated circuit including a dummy gate structure and method for...

Inline monitoring of transistor-to-transistor critical dimension

Semiconductor structure with back-gate switching

Process monitoring for gate cut mask

Wafer with SOI structure having a buried insulating multilayer stru...

Device comprising a plurality of FDSOI static random-access memory...

Memory cell assembly including an avoid disturb cell

Device including an array of memory cells and well contact areas, a...

Device comprising a plurality of static random access memory cells...

Hybrid read scheme for multi-level data

Non-volatile memory with predictive programming

Patents Applicationslast 30 patents

IC STRUCTURE FOR CONNECTED CAPACITANCES AND METHOD OF FORMING SAME

SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION

SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION

EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL

EXTENDED-DRAIN FIELD-EFFECT TRANSISTORS INCLUDING A FLOATING GATE

IC PRODUCT WITH A NOVEL BIT CELL DESIGN AND A MEMORY ARRAY COMPRISI...

DEEP FENCE ISOLATION FOR LOGIC CELLS

DUAL-DEPTH STI CAVITY EXTENSION AND METHOD OF PRODUCTION THEREOF

HIGH-VOLTAGE TRANSISTOR DEVICE WITH THICK GATE INSULATION LAYERS

SEMICONDUCTOR DEVICE INCLUDING FDSOI TRANSISTORS WITH COMPACT GROUN...

FINFET SRAM LAYOUT AND METHOD OF MAKING THE SAME

ALIGNMENT KEY DESIGN RULE CHECK FOR CORRECT PLACEMENT OF ABUTTING C...

HIGH-VOLTAGE TRANSISTOR DEVICE WITH THICK GATE INSULATION LAYERS

HIGH VOLTAGE TRANSISTOR USING BURIED INSULATING LAYER AS GATE DIELE...

SEMICONDUCTOR STRUCTURE WITH BACK-GATE SWITCHING

METHODS FOR FORMING INTEGRATED CIRCUITS THAT INCLUDE A DUMMY GATE S...

INLINE MONITORING OF TRANSISTOR-TO-TRANSISTOR CRITICAL DIMENSION

WAFER WITH SOI STRUCTURE HAVING A BURIED INSULATING MULTILAYER STRU...

DEVICE COMPRISING A PLURALITY OF FDSOI STATIC RANDOM-ACCESS MEMORY...

DEVICE INCLUDING AN ARRAY OF MEMORY CELLS AND WELL CONTACT AREAS, A...

DEVICE COMPRISING A PLURALITY OF STATIC RANDOM ACCESS MEMORY CELLS...

MEMORY CELL ASSEMBLY INCLUDING AN AVOID DISTURB CELL

Hybrid Read Scheme for Multi-Level Data

NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING