Nihaar N. Mahatme

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Magnetoresistive random access memory (MRAM) with end of life margi...
- Patent number 12,094,510
- Issue date Sep 17, 2024
- NXP USA, INC.
- Anirban Roy
- G11 - INFORMATION STORAGE
Information Patent Grant
Reusing memory arrays for physically unclonable function (PUF) gene...
- Patent number 12,001,674
- Issue date Jun 4, 2024
- NXP USA, INC.
- Nihaar N. Mahatme
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packaged semiconductor device assembly
- Patent number 11,908,784
- Issue date Feb 20, 2024
- NXP USA, INC.
- Akhilesh Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Error rate reduction in a non-volatile memory (NVM), including magn...
- Patent number 11,755,411
- Issue date Sep 12, 2023
- NXP USA, INC.
- Anirban Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error rate reduction in a non-volatile memory (NVM), including magn...
- Patent number 11,379,307
- Issue date Jul 5, 2022
- NXP USA, INC.
- Anirban Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SRAM based physically unclonable function and method for generating...
- Patent number 11,277,271
- Issue date Mar 15, 2022
- NXP USA, INC.
- Glenn Charles Abeln
- G11 - INFORMATION STORAGE
Information Patent Grant
Physically unclonable function having source bias transistors
- Patent number 11,233,663
- Issue date Jan 25, 2022
- NXP USA, INC.
- Alexander Hoefler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Packaged integrated circuit having a photodiode and a resistive memory
- Patent number 11,222,679
- Issue date Jan 11, 2022
- NXP USA, INC.
- Nihaar N. Mahatme
- G11 - INFORMATION STORAGE
Information Patent Grant
Glitch profiling in an integrated circuit
- Patent number 11,164,648
- Issue date Nov 2, 2021
- NXP USA, INC.
- Nihaar N. Mahatme
- G01 - MEASURING TESTING
Information Patent Grant
Data processing system and method for generating a digital code wit...
- Patent number 11,056,161
- Issue date Jul 6, 2021
- NXP USA, INC.
- Nihaar N. Mahatme
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Tamper protection of memory devices on an integrated circuit
- Patent number 10,978,123
- Issue date Apr 13, 2021
- NXP USA, INC.
- Geoffrey Mark Lees
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Magnetic attack detection in a magnetic random access memory (MRAM)
- Patent number 10,921,390
- Issue date Feb 16, 2021
- NXP USA, INC.
- Nihaar N. Mahatme
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM based physically unclonable function and method for generating...
- Patent number 10,734,047
- Issue date Aug 4, 2020
- NXP USA, INC.
- Nihaar N. Mahatme
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM memory with OTP cells
- Patent number 10,699,764
- Issue date Jun 30, 2020
- NXP USA, INC.
- Anirban Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Physically unclonable function and method for generating a digital...
- Patent number 10,574,469
- Issue date Feb 25, 2020
- NXP USA, INC.
- Brad John Garni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Magnetic attack detection in a magnetic random access memory (MRAM)
- Patent number 10,529,400
- Issue date Jan 7, 2020
- NXP USA, INC.
- Nihaar N. Mahatme
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system having a source bias circuit
- Patent number 10,446,225
- Issue date Oct 15, 2019
- NXP USA, INC.
- Alexander Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
SRAM based physically unclonable function and method for generating...
- Patent number 9,947,391
- Issue date Apr 17, 2018
- NXP USA, INC.
- Nihaar N. Mahatme
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for determining feasibility of memory operatin...
- Patent number 9,817,601
- Issue date Nov 14, 2017
- NXP USA, INC.
- Shayan Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Devices and methods with capacitive storage for latch redundancy
- Patent number 9,559,671
- Issue date Jan 31, 2017
- NXP USA, INC.
- Srikanth Jagannathan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MEMORY WITH ONE-TIME PROGRAMMABLE (OTP) CELLS
- Publication number 20240321372
- Publication date Sep 26, 2024
- NXP USA, Inc.
- Anirban Roy
- G11 - INFORMATION STORAGE
Information Patent Application
REUSING MEMORY ARRAYS FOR PHYSICALLY UNCLONABLE FUNCTION (PUF) GENE...
- Publication number 20240143167
- Publication date May 2, 2024
- NXP USA, Inc.
- Nihaar N. Mahatme
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) WITH END OF LIFE MARGI...
- Publication number 20230410870
- Publication date Dec 21, 2023
- NXP USA, Inc.
- Anirban Roy
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR RATE REDUCTION IN A NON-VOLATILE MEMORY (NVM), INCLUDING MAGN...
- Publication number 20220327020
- Publication date Oct 13, 2022
- Anirban Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR RATE REDUCTION IN A NON-VOLATILE MEMORY (NVM), INCLUDING MAGN...
- Publication number 20220179740
- Publication date Jun 9, 2022
- NXP USA, Inc.
- Anirban Roy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGED SEMICONDUCTOR DEVICE ASSEMBLY
- Publication number 20220093499
- Publication date Mar 24, 2022
- NXP USA, Inc.
- Akhilesh Kumar Singh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHYSICALLY UNCLONABLE FUNCTION HAVING SOURCE BIAS TRANSISTORS
- Publication number 20220029834
- Publication date Jan 27, 2022
- NXP USA, Inc.
- Alexander Hoefler
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PACKAGED INTEGRATED CIRCUIT HAVING A PHOTODIODE AND A RESISTIVE MEMORY
- Publication number 20210082488
- Publication date Mar 18, 2021
- NXP USA, Inc.
- Nihaar N. Mahatme
- G11 - INFORMATION STORAGE
Information Patent Application
SRAM BASED PHYSICALLY UNCLONABLE FUNCTION AND METHOD FOR GENERATING...
- Publication number 20210036872
- Publication date Feb 4, 2021
- NXP USA, Inc.
- Glenn Charles Abeln
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PROCESSING SYSTEM AND METHOD FOR GENERATING A DIGITAL CODE WIT...
- Publication number 20210027814
- Publication date Jan 28, 2021
- NXP USA, Inc.
- Nihaar N. Mahatme
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
GLITCH PROFILING IN AN INTEGRATED CIRCUIT
- Publication number 20200402602
- Publication date Dec 24, 2020
- NXP USA, Inc.
- Nihaar N. Mahatme
- G01 - MEASURING TESTING
Information Patent Application
MAGNETIC ATTACK DETECTION IN A MAGNETIC RANDOM ACCESS MEMORY (MRAM)
- Publication number 20200379063
- Publication date Dec 3, 2020
- NXP USA, Inc.
- Nihaar N. Mahatme
- G01 - MEASURING TESTING
Information Patent Application
SRAM BASED PHYSICALLY UNCLONABLE FUNCTION AND METHOD FOR GENERATING...
- Publication number 20200243122
- Publication date Jul 30, 2020
- NXP USA, Inc.
- NIHAAR N. MAHATME
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MRAM MEMORY WITH OTP CELLS
- Publication number 20200194048
- Publication date Jun 18, 2020
- NXP USA, Inc.
- Anirban Roy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TAMPER PROTECTION OF MEMORY DEVICES ON AN INTEGRATED CIRCUIT
- Publication number 20200176044
- Publication date Jun 4, 2020
- NXP USA, Inc.
- GEOFFREY MARK LEES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAGNETIC ATTACK DETECTION IN A MAGNETIC RANDOM ACCESS MEMORY (MRAM)
- Publication number 20200035284
- Publication date Jan 30, 2020
- NXP USA, Inc.
- NIHAAR N. MAHATME
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM HAVING A SOURCE BIAS CIRCUIT
- Publication number 20190333575
- Publication date Oct 31, 2019
- NXP USA, Inc.
- Alexander Hoefler
- G11 - INFORMATION STORAGE

Nihaar N. Mahatme

Person

Patents Grantslast 30 patents

Magnetoresistive random access memory (MRAM) with end of life margi...

Reusing memory arrays for physically unclonable function (PUF) gene...

Packaged semiconductor device assembly

Error rate reduction in a non-volatile memory (NVM), including magn...

Error rate reduction in a non-volatile memory (NVM), including magn...

SRAM based physically unclonable function and method for generating...

Physically unclonable function having source bias transistors

Packaged integrated circuit having a photodiode and a resistive memory

Glitch profiling in an integrated circuit

Data processing system and method for generating a digital code wit...

Tamper protection of memory devices on an integrated circuit

Magnetic attack detection in a magnetic random access memory (MRAM)

SRAM based physically unclonable function and method for generating...

MRAM memory with OTP cells

Physically unclonable function and method for generating a digital...

Magnetic attack detection in a magnetic random access memory (MRAM)

Memory system having a source bias circuit

SRAM based physically unclonable function and method for generating...

Method and apparatus for determining feasibility of memory operatin...

Devices and methods with capacitive storage for latch redundancy

Patents Applicationslast 30 patents

MEMORY WITH ONE-TIME PROGRAMMABLE (OTP) CELLS

REUSING MEMORY ARRAYS FOR PHYSICALLY UNCLONABLE FUNCTION (PUF) GENE...

MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) WITH END OF LIFE MARGI...

ERROR RATE REDUCTION IN A NON-VOLATILE MEMORY (NVM), INCLUDING MAGN...

ERROR RATE REDUCTION IN A NON-VOLATILE MEMORY (NVM), INCLUDING MAGN...

PACKAGED SEMICONDUCTOR DEVICE ASSEMBLY

PHYSICALLY UNCLONABLE FUNCTION HAVING SOURCE BIAS TRANSISTORS

PACKAGED INTEGRATED CIRCUIT HAVING A PHOTODIODE AND A RESISTIVE MEMORY

SRAM BASED PHYSICALLY UNCLONABLE FUNCTION AND METHOD FOR GENERATING...

DATA PROCESSING SYSTEM AND METHOD FOR GENERATING A DIGITAL CODE WIT...

GLITCH PROFILING IN AN INTEGRATED CIRCUIT

MAGNETIC ATTACK DETECTION IN A MAGNETIC RANDOM ACCESS MEMORY (MRAM)

SRAM BASED PHYSICALLY UNCLONABLE FUNCTION AND METHOD FOR GENERATING...

MRAM MEMORY WITH OTP CELLS

TAMPER PROTECTION OF MEMORY DEVICES ON AN INTEGRATED CIRCUIT

MAGNETIC ATTACK DETECTION IN A MAGNETIC RANDOM ACCESS MEMORY (MRAM)

MEMORY SYSTEM HAVING A SOURCE BIAS CIRCUIT