Nikhil Mazumder

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Delay locked loop for an FPGA architecture
- Patent number 7,941,685
- Issue date May 10, 2011
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop for an FPGA architecture
- Patent number 7,484,113
- Issue date Jan 27, 2009
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop for and FPGA architecture
- Patent number 7,171,575
- Issue date Jan 30, 2007
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop for an FPGA architecture
- Patent number 6,976,185
- Issue date Dec 13, 2005
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop for an FPGA architecture
- Patent number 6,718,477
- Issue date Apr 6, 2004
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for mapping test signals of an integrated circuit
- Patent number 5,369,643
- Issue date Nov 29, 1994
- Intel Corporation
- Farid Rastgar
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
DELAY LOCKED LOOP FOR AN FPGA ARCHITECTURE
- Publication number 20090094475
- Publication date Apr 9, 2009
- Actel Corporation
- William C. Plants
- G06 - COMPUTING CALCULATING COUNTING