Nikita Naresh

Person

Bangalore, IN

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for parallel memory test
- Patent number 12,142,337
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Nitesh Mishra
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan chain self-testing of lockstep cores on reset
- Patent number 11,852,683
- Issue date Dec 26, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
System and method for parallel memory test
- Patent number 11,776,656
- Issue date Oct 3, 2023
- Texas Instruments Incorporated
- Nitesh Mishra
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for low power memory test
- Patent number 11,715,544
- Issue date Aug 1, 2023
- Texas Instruments Incorporated
- Nitesh Mishra
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan chain self-testing of lockstep cores on reset
- Patent number 11,555,853
- Issue date Jan 17, 2023
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Testing read-only memory using memory built-in self-test controller
- Patent number 11,521,698
- Issue date Dec 6, 2022
- Texas Instruments Incorporated
- Prakash Narayanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan chain self-testing of lockstep cores on reset
- Patent number 10,866,280
- Issue date Dec 15, 2020
- Texas Instruments Incorporated
- Prakash Narayanan
- G01 - MEASURING TESTING
Information Patent Grant
Testing read-only memory using memory built-in self-test controller
- Patent number 10,818,374
- Issue date Oct 27, 2020
- Texas Instruments Incorporated
- Prakash Narayanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area efficient parallel test data path for embedded memories
- Patent number 10,460,821
- Issue date Oct 29, 2019
- Texas Instruments Incorporated
- Prakash Narayanan
- G11 - INFORMATION STORAGE
Information Patent Grant
Area efficient parallel test data path for embedded memories
- Patent number 9,899,103
- Issue date Feb 20, 2018
- Texas Instruments Incorporated
- Prakash Narayanan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR PARALLEL MEMORY TEST
- Publication number 20230402124
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Nitesh MISHRA
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET
- Publication number 20230152373
- Publication date May 18, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR LOW POWER MEMORY TEST
- Publication number 20220415423
- Publication date Dec 29, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Nitesh MISHRA
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS FOR USING SCAN OPERATIONS TO PROTECT SECURE A...
- Publication number 20220358230
- Publication date Nov 10, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PARALLEL MEMORY TEST
- Publication number 20220343995
- Publication date Oct 27, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Nitesh MISHRA
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET
- Publication number 20210055345
- Publication date Feb 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER
- Publication number 20200388346
- Publication date Dec 10, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET
- Publication number 20200309851
- Publication date Oct 1, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G01 - MEASURING TESTING
Information Patent Application
TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER
- Publication number 20200135290
- Publication date Apr 30, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Prakash NARAYANAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES
- Publication number 20180174663
- Publication date Jun 21, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G11 - INFORMATION STORAGE
Information Patent Application
AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDED MEMORIES
- Publication number 20170157524
- Publication date Jun 8, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- A63 - SPORTS GAMES AMUSEMENTS
Information Patent Application
AREA-EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES
- Publication number 20170125125
- Publication date May 4, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Prakash Narayanan
- G11 - INFORMATION STORAGE

Nikita Naresh

Person

Patents Grantslast 30 patents

System and method for parallel memory test

Scan chain self-testing of lockstep cores on reset

System and method for parallel memory test

System and method for low power memory test

Scan chain self-testing of lockstep cores on reset

Testing read-only memory using memory built-in self-test controller

Scan chain self-testing of lockstep cores on reset

Testing read-only memory using memory built-in self-test controller

Area efficient parallel test data path for embedded memories

Area efficient parallel test data path for embedded memories

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR PARALLEL MEMORY TEST

SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET

SYSTEM AND METHOD FOR LOW POWER MEMORY TEST

METHODS AND APPARATUS FOR USING SCAN OPERATIONS TO PROTECT SECURE A...

SYSTEM AND METHOD FOR PARALLEL MEMORY TEST

SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET

TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER

SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET

TESTING READ-ONLY MEMORY USING MEMORY BUILT-IN SELF-TEST CONTROLLER

AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES

AREA EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDED MEMORIES

AREA-EFFICIENT PARALLEL TEST DATA PATH FOR EMBEDDED MEMORIES