Nilanjan Mukherjee

Person

Wilsonville, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Universal compactor architecture for testing circuits
- Patent number 11,815,555
- Issue date Nov 14, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Grant
Multizone quadrilateral mesh generator for high mesh quality and is...
- Patent number 11,763,526
- Issue date Sep 19, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trajectory-optimized test pattern generation for built-in self-test
- Patent number 11,585,853
- Issue date Feb 21, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Grant
Deterministic stellar built-in self test
- Patent number 11,555,854
- Issue date Jan 17, 2023
- SIEMENS INDUSTRY SOFTWARE INC.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Grant
Feature based abstraction and meshing
- Patent number 11,494,982
- Issue date Nov 8, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Jonathan Makem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout-friendly test pattern decompressor
- Patent number 11,232,246
- Issue date Jan 25, 2022
- SIEMENS INDUSTRY SOFTWARE INC.
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for element quality improvement in 3D quadrilater...
- Patent number 11,126,766
- Issue date Sep 21, 2021
- SIEMENS INDUSTRY SOFTWARE INC.
- Jonathan Makem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan cell architecture for improving test coverage and reducing tes...
- Patent number 10,963,612
- Issue date Mar 30, 2021
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mesh generation system and method
- Patent number 10,956,625
- Issue date Mar 23, 2021
- SIEMENS INDUSTRY SOFTWARE INC.
- Jonathan Makem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test scheduling and test access in test compression environment
- Patent number 10,955,460
- Issue date Mar 23, 2021
- Mentor Graphics Corporation
- Mark Kassab
- G01 - MEASURING TESTING
Information Patent Grant
Test application time reduction using capture-per-cycle test points
- Patent number 10,509,072
- Issue date Dec 17, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test point insertion for low test pattern counts
- Patent number 10,444,282
- Issue date Oct 15, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test point-enhanced hardware security
- Patent number 10,361,873
- Issue date Jul 23, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Continuous application and decompression of test patterns and selec...
- Patent number 10,234,506
- Issue date Mar 19, 2019
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 9,874,606
- Issue date Jan 23, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Continuous application and decompression of test patterns and selec...
- Patent number 9,664,739
- Issue date May 30, 2017
- Mentor Graphics Corporation
- Janusz Rasjki
- G01 - MEASURING TESTING
Information Patent Grant
Isometric test compression with low toggling activity
- Patent number 9,651,622
- Issue date May 16, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 9,377,508
- Issue date Jun 28, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
On-chip comparison and response collection tools and techniques
- Patent number 9,250,287
- Issue date Feb 2, 2016
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Grant
Continuous application and decompression of test patterns and selec...
- Patent number 9,134,370
- Issue date Sep 15, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Test scheduling with pattern-independent test access mechanism
- Patent number 9,088,522
- Issue date Jul 21, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System, method, and computer program product for smoothing
- Patent number 9,082,220
- Issue date Jul 14, 2015
- Siemens Product Lifecycle Management Software Inc.
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip comparison and response collection tools and techniques
- Patent number 8,914,694
- Issue date Dec 16, 2014
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Grant
Low power compression of incompatible test cubes
- Patent number 8,832,512
- Issue date Sep 9, 2014
- Mentor Graphics Corporation
- Dariusz Czysz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selective per-cycle masking of scan chains for system level test
- Patent number 8,726,113
- Issue date May 13, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Scan test application through high-speed serial input/outputs
- Patent number 8,726,112
- Issue date May 13, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
Continuous application and decompression of test patterns and selec...
- Patent number 8,533,547
- Issue date Sep 10, 2013
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
At-speed scan testing with controlled switching activity
- Patent number 8,499,209
- Issue date Jul 30, 2013
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Grant
On-chip comparison and response collection tools and techniques
- Patent number 8,418,007
- Issue date Apr 9, 2013
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Grant
Fault diagnosis for non-volatile memories
- Patent number 8,356,222
- Issue date Jan 15, 2013
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
IMPRINT-BASED MESH GENERATION FOR COMPUTER-AIDED DESIGN (CAD) OBJECTS
- Publication number 20240265171
- Publication date Aug 8, 2024
- Siemens Industry Software Inc.
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test Generation for Structurally Similar Circuits
- Publication number 20240160823
- Publication date May 16, 2024
- Siemens Industry Software Inc.
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIVERSAL COMPACTOR ARCHITECTURE FOR TESTING CIRCUITS
- Publication number 20220308110
- Publication date Sep 29, 2022
- Siemens Industry Software Inc.
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Application
MODIFYING A FINITE ELEMENT MESH
- Publication number 20220067242
- Publication date Mar 3, 2022
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINISTIC STELLAR BUILT-IN SELF TEST
- Publication number 20210373077
- Publication date Dec 2, 2021
- Yingdi Liu
- G01 - MEASURING TESTING
Information Patent Application
FEATURE BASED ABSTRACTION AND MESHING
- Publication number 20210335042
- Publication date Oct 28, 2021
- Siemens Industry Software Inc.
- Jonathan Makem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIZONE QUADRILATERAL MESH GENERATOR FOR HIGH MESH QUALITY AND IS...
- Publication number 20210327139
- Publication date Oct 21, 2021
- Siemens Industry Software Inc.
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Trajectory-Optimized Test Pattern Generation for Built-In Self-Test
- Publication number 20210156918
- Publication date May 27, 2021
- Mentor Graphics Corporation
- Grzegorz Mrugalski
- G01 - MEASURING TESTING
Information Patent Application
Layout-Friendly Test Pattern Decompressor
- Publication number 20210150112
- Publication date May 20, 2021
- Mentor Graphics Corporation
- Yu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ELEMENT QUALITY IMPROVEMENT IN 3D QUADRILATER...
- Publication number 20210103685
- Publication date Apr 8, 2021
- Siemens Product Lifecycle Management Software Inc.
- Jonathan Makem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scan Cell Architecture For Improving Test Coverage And Reducing Tes...
- Publication number 20200327268
- Publication date Oct 15, 2020
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test Application Time Reduction Using Capture-Per-Cycle Test Points
- Publication number 20180252768
- Publication date Sep 6, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20180143249
- Publication date May 24, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...
- Publication number 20180017622
- Publication date Jan 18, 2018
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
POWER-ON SELF-TEST AND IN-SYSTEM TEST
- Publication number 20170205462
- Publication date Jul 20, 2017
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Application
Test Point-Enhanced Hardware Security
- Publication number 20170141930
- Publication date May 18, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
MESH GENERATION SYSTEM AND METHOD
- Publication number 20170061037
- Publication date Mar 2, 2017
- Siemens Product Lifecycle Management Software Inc.
- Jonathan Makem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20170052227
- Publication date Feb 23, 2017
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
Test Point Insertion For Low Test Pattern Counts
- Publication number 20160109517
- Publication date Apr 21, 2016
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...
- Publication number 20160003907
- Publication date Jan 7, 2016
- Mentor Graphics Corporation
- Janusz Rasjki
- G01 - MEASURING TESTING
Information Patent Application
Test Scheduling and Test Access in Test Compression Environment
- Publication number 20150285854
- Publication date Oct 8, 2015
- Mark A. Kassab
- G01 - MEASURING TESTING
Information Patent Application
Isometric Test Compression With Low Toggling Activity
- Publication number 20150253385
- Publication date Sep 10, 2015
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES
- Publication number 20150160290
- Publication date Jun 11, 2015
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20140229779
- Publication date Aug 14, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...
- Publication number 20140006888
- Publication date Jan 2, 2014
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES
- Publication number 20130305107
- Publication date Nov 14, 2013
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Application
Test Scheduling With Pattern-Independent Test Access Mechanism
- Publication number 20130290795
- Publication date Oct 31, 2013
- Mentor Graphics Corporation
- Janusz Rajski
- G01 - MEASURING TESTING
Information Patent Application
SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST
- Publication number 20120210181
- Publication date Aug 16, 2012
- Mentor Graphics Corporation
- Janusz Rajski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES
- Publication number 20110231722
- Publication date Sep 22, 2011
- Mentor Graphics Corporation
- Nilanjan Mukherjee
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER COMPRESSION OF INCOMPATIBLE TEST CUBES
- Publication number 20110231721
- Publication date Sep 22, 2011
- DARIUSZ CZYSZ
- G06 - COMPUTING CALCULATING COUNTING

Nilanjan Mukherjee

Person

Patents Grantslast 30 patents

Universal compactor architecture for testing circuits

Multizone quadrilateral mesh generator for high mesh quality and is...

Trajectory-optimized test pattern generation for built-in self-test

Deterministic stellar built-in self test

Feature based abstraction and meshing

Layout-friendly test pattern decompressor

System and method for element quality improvement in 3D quadrilater...

Scan cell architecture for improving test coverage and reducing tes...

Mesh generation system and method

Test scheduling and test access in test compression environment

Test application time reduction using capture-per-cycle test points

Test point insertion for low test pattern counts

Test point-enhanced hardware security

Continuous application and decompression of test patterns and selec...

Selective per-cycle masking of scan chains for system level test

Continuous application and decompression of test patterns and selec...

Isometric test compression with low toggling activity

Selective per-cycle masking of scan chains for system level test

On-chip comparison and response collection tools and techniques

Continuous application and decompression of test patterns and selec...

Test scheduling with pattern-independent test access mechanism

System, method, and computer program product for smoothing

On-chip comparison and response collection tools and techniques

Low power compression of incompatible test cubes

Selective per-cycle masking of scan chains for system level test

Scan test application through high-speed serial input/outputs

Continuous application and decompression of test patterns and selec...

At-speed scan testing with controlled switching activity

On-chip comparison and response collection tools and techniques

Fault diagnosis for non-volatile memories

Patents Applicationslast 30 patents

IMPRINT-BASED MESH GENERATION FOR COMPUTER-AIDED DESIGN (CAD) OBJECTS

Test Generation for Structurally Similar Circuits

UNIVERSAL COMPACTOR ARCHITECTURE FOR TESTING CIRCUITS

MODIFYING A FINITE ELEMENT MESH

DETERMINISTIC STELLAR BUILT-IN SELF TEST

FEATURE BASED ABSTRACTION AND MESHING

MULTIZONE QUADRILATERAL MESH GENERATOR FOR HIGH MESH QUALITY AND IS...

Trajectory-Optimized Test Pattern Generation for Built-In Self-Test

Layout-Friendly Test Pattern Decompressor

SYSTEM AND METHOD FOR ELEMENT QUALITY IMPROVEMENT IN 3D QUADRILATER...

Scan Cell Architecture For Improving Test Coverage And Reducing Tes...

Test Application Time Reduction Using Capture-Per-Cycle Test Points

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...

POWER-ON SELF-TEST AND IN-SYSTEM TEST

Test Point-Enhanced Hardware Security

MESH GENERATION SYSTEM AND METHOD

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

Test Point Insertion For Low Test Pattern Counts

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...

Test Scheduling and Test Access in Test Compression Environment

Isometric Test Compression With Low Toggling Activity

ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

CONTINUOUS APPLICATION AND DECOMPRESSION OF TEST PATTERNS AND SELEC...

ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES

Test Scheduling With Pattern-Independent Test Access Mechanism

SELECTIVE PER-CYCLE MASKING OF SCAN CHAINS FOR SYSTEM LEVEL TEST

ON-CHIP COMPARISON AND RESPONSE COLLECTION TOOLS AND TECHNIQUES

LOW POWER COMPRESSION OF INCOMPATIBLE TEST CUBES