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Nipun Mahajan
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New Delhi, IN
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Patents Grants
last 30 patents
Information
Patent Grant
System and method for facilitating built-in self-test of system-on-...
Patent number
11,513,153
Issue date
Nov 29, 2022
NXP USA, INC.
Rohan Poudel
G01 - MEASURING TESTING
Information
Patent Grant
Error management system for system-on-chip
Patent number
11,461,205
Issue date
Oct 4, 2022
NXP B.V.
Neha Bagri
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Structural testing of integrated circuits
Patent number
9,599,673
Issue date
Mar 21, 2017
FREESCALE SEMICONDUCTOR, INC.
Anurag Jindal
G01 - MEASURING TESTING
Information
Patent Grant
Built-in self test (BIST) with clock control
Patent number
9,298,572
Issue date
Mar 29, 2016
FREESCALE SEMICONDUCTOR, INC.
Nisar Ahmed
G01 - MEASURING TESTING
Information
Patent Grant
System and method for determining power leakage of electronic circu...
Patent number
8,793,641
Issue date
Jul 29, 2014
FREESCALE SEMICONDUCTOR, INC.
Amit Roy
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
System and method for debugging scan chains
Patent number
8,458,541
Issue date
Jun 4, 2013
FREESCALE SEMICONDUCTOR, INC.
Sandeep Jain
G01 - MEASURING TESTING
Patents Applications
last 30 patents
Information
Patent Application
SYSTEM AND METHOD FOR FACILITATING BUILT-IN SELF-TEST OF SYSTEM-ON-...
Publication number
20220334181
Publication date
Oct 20, 2022
NXP USA, Inc.
Rohan Poudel
G01 - MEASURING TESTING
Information
Patent Application
STRUCTURAL TESTING OF INTEGRATED CIRCUITS
Publication number
20160109514
Publication date
Apr 21, 2016
Anurag Jindal
G01 - MEASURING TESTING
Information
Patent Application
BUILT-IN SELF TEST (BIST) WITH CLOCK CONTROL
Publication number
20140281778
Publication date
Sep 18, 2014
Nisar Ahmed
G01 - MEASURING TESTING
Information
Patent Application
SYSTEM AND METHOD FOR DEBUGGING SCAN CHAINS
Publication number
20120246531
Publication date
Sep 27, 2012
FREESCALE SEMICONDUCTOR, INC.
Sandeep Jain
G01 - MEASURING TESTING