Niranjan Behera

Person

Newark, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sequential delay enabler timer circuit for low voltage operation fo...
- Patent number 11,670,361
- Issue date Jun 6, 2023
- Synopsys, Inc.
- Moon-Hae Son
- G11 - INFORMATION STORAGE
Information Patent Grant
Using sense amplifier as a write booster in memory operating with a...
- Patent number 9,966,131
- Issue date May 8, 2018
- Synopsys, Inc.
- Dharmesh Kumar Sonkar
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for reducing memory array leakage in high capac...
- Patent number 7,940,550
- Issue date May 10, 2011
- Synopsys, Inc.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Grant
Statistical yield of a system-on-a-chip
- Patent number 7,904,766
- Issue date Mar 8, 2011
- Synopsys, Inc.
- Niranjan Behera
Information Patent Grant
System and method for repairing a memory
- Patent number 7,788,551
- Issue date Aug 31, 2010
- Virage Logic Corp.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing a memory
- Patent number 7,539,590
- Issue date May 26, 2009
- Virage Logic Corp.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for repairing a memory
- Patent number 7,415,641
- Issue date Aug 19, 2008
- Virage Logic Corp.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for testing a dual-port memory at speed in a stre...
- Patent number 7,139,204
- Issue date Nov 21, 2006
- Virage Logic Corporation
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing a memory
- Patent number 7,031,866
- Issue date Apr 18, 2006
- Virage Logic Corp.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to reduce the amount of redundant memory colum...
- Patent number 6,646,933
- Issue date Nov 11, 2003
- Virage Logic Corporation
- Alexander Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus to change the amount of redundant memory colum...
- Patent number 6,519,202
- Issue date Feb 11, 2003
- Virage Logic Corporation
- Alexander Shubat
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory having a redundancy scheme to allow one fuse to blow per fau...
- Patent number 6,396,760
- Issue date May 28, 2002
- Virage Logic Corporation
- Niranjan Behera
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
REDUCED CIRCUIT AREA MEMORY DEVICE WITH A HALF-WORD MEMORY ARCHITEC...
- Publication number 20240371416
- Publication date Nov 7, 2024
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
SEQUENTIAL DELAY ENABLER TIMER CIRCUIT FOR LOW VOLTAGE OPERATION FO...
- Publication number 20220020420
- Publication date Jan 20, 2022
- Synopsys, Inc.
- Moon-Hae Son
- G11 - INFORMATION STORAGE
Information Patent Application
Using Sense Amplifier As A Write Booster In Memory Operating With A...
- Publication number 20170053695
- Publication date Feb 23, 2017
- Synopsys, Inc.
- Dharmesh Kumar Sonkar
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPAC...
- Publication number 20110063893
- Publication date Mar 17, 2011
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Application
System and Method for Repairing a Memory
- Publication number 20080301507
- Publication date Dec 4, 2008
- VIRAGE LOGIC CORP.
- Niranjan Behera
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for testing a memory
- Publication number 20060190208
- Publication date Aug 24, 2006
- Virage Logic Corp.
- Niranjan Behera
- G11 - INFORMATION STORAGE

Niranjan Behera

Person

Patents Grantslast 30 patents

Sequential delay enabler timer circuit for low voltage operation fo...

Using sense amplifier as a write booster in memory operating with a...

Systems and methods for reducing memory array leakage in high capac...

Statistical yield of a system-on-a-chip

System and method for repairing a memory

System and method for testing a memory

System and method for repairing a memory

Method and system for testing a dual-port memory at speed in a stre...

System and method for testing a memory

Method and apparatus to reduce the amount of redundant memory colum...

Method and apparatus to change the amount of redundant memory colum...

Memory having a redundancy scheme to allow one fuse to blow per fau...

Patents Applicationslast 30 patents

REDUCED CIRCUIT AREA MEMORY DEVICE WITH A HALF-WORD MEMORY ARCHITEC...

SEQUENTIAL DELAY ENABLER TIMER CIRCUIT FOR LOW VOLTAGE OPERATION FO...

Using Sense Amplifier As A Write Booster In Memory Operating With A...

SYSTEMS AND METHODS FOR REDUCING MEMORY ARRAY LEAKAGE IN HIGH CAPAC...

System and Method for Repairing a Memory

System and method for testing a memory