Niravkumar Patel

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit chip testing interface with reduced signal wires
- Patent number 11,860,228
- Issue date Jan 2, 2024
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G01 - MEASURING TESTING
Information Patent Grant
Hybrid synchronous and asynchronous control for scan-based testing
- Patent number 11,755,804
- Issue date Sep 12, 2023
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable scan architecture for multi-circuit block arrays
- Patent number 11,639,962
- Issue date May 2, 2023
- Xilinx, Inc.
- Niravkumar Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable dynamic clock stretch for at-speed debugging of integr...
- Patent number 11,290,095
- Issue date Mar 29, 2022
- Xilinx, Inc.
- Niravkumar Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit architecture for expanded design for testability functionality
- Patent number 11,263,377
- Issue date Mar 1, 2022
- Xilinx, Inc.
- Amitava Majumdar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT CHIP TESTING INTERFACE WITH REDUCED SIGNAL WIRES
- Publication number 20230366929
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Albert Shih-Huai LIN
- G01 - MEASURING TESTING
Information Patent Application
HYBRID SYNCHRONOUS AND ASYNCHRONOUS CONTROL FOR SCAN-BASED TESTING
- Publication number 20230205959
- Publication date Jun 29, 2023
- Xilinx, Inc.
- Albert Shih-Huai Lin
- G06 - COMPUTING CALCULATING COUNTING