Nishath K. Verghese

Follow

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Timing, noise, and power analysis of integrated circuits
- Patent number 8,225,248
- Issue date Jul 17, 2012
- Cadence Design Systems, Inc.
- Haizhou Chen
- G05 - CONTROLLING REGULATING
Information Patent Grant
Method to analyze and correct dynamic power grid variations in ICs
- Patent number 7,844,438
- Issue date Nov 30, 2010
- Cadence Design Systems, Inc.
- Nishath Verghese
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling device variations in integrated circuit design
- Patent number 7,673,260
- Issue date Mar 2, 2010
- Cadence Design Systems, Inc.
- Haizhou Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Robust calculation of crosstalk delay change in integrated circuit...
- Patent number 7,359,843
- Issue date Apr 15, 2008
- Cadence Design Systems, Inc.
- Igor Keller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for modeling variation of circuit parameters in d...
- Patent number 7,310,792
- Issue date Dec 18, 2007
- Cadence Design Systems, Inc.
- Nishath K. Verghese
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Modeling device variations in integrated circuit design
- Publication number 20070099314
- Publication date May 3, 2007
- Haizhou Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing, noise, and power analysis of integrated circuits
- Publication number 20070094623
- Publication date Apr 26, 2007
- Haizhou Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system for modeling variation of circuit parameters in d...
- Publication number 20050278671
- Publication date Dec 15, 2005
- Cadence Design Systems, Inc.
- Nishath K. Verghese
- G06 - COMPUTING CALCULATING COUNTING