Nishu Kohli

Person

Noida, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Automatic test-pattern generation for memory-shadow-logic testing
- Patent number 10,535,416
- Issue date Jan 14, 2020
- STMicroelectronics International N.V.
- Nishu Kohli
- G01 - MEASURING TESTING
Information Patent Grant
Automatic test-pattern generation for memory-shadow-logic testing
- Patent number 9,812,219
- Issue date Nov 7, 2017
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Selective dual cycle write operation for a self-timed memory
- Patent number 9,324,414
- Issue date Apr 26, 2016
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable delay introducing circuit in self timed memory
- Patent number 9,147,453
- Issue date Sep 29, 2015
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic test-pattern generation for memory-shadow-logic testing
- Patent number 9,003,255
- Issue date Apr 7, 2015
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable delay introducing circuit in self-timed memory
- Patent number 8,963,053
- Issue date Feb 24, 2015
- STMicroelectronics Pvt. Ltd.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
XY ternary content addressable memory (TCAM) cell and array
- Patent number 8,929,115
- Issue date Jan 6, 2015
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual clock edge triggered memory
- Patent number 8,913,457
- Issue date Dec 16, 2014
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Read self timing circuitry for self-timed memory
- Patent number 8,854,901
- Issue date Oct 7, 2014
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Write self timing circuitry for self-timed memory
- Patent number 8,854,902
- Issue date Oct 7, 2014
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual clock edge triggered memory
- Patent number 8,730,756
- Issue date May 20, 2014
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual port register file memory cell with reduced susceptibility to...
- Patent number 8,681,534
- Issue date Mar 25, 2014
- STMicroelectronics International N.V.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable delay introducing circuit in self timed memory
- Patent number 8,138,455
- Issue date Mar 20, 2012
- STMicroelectronics Pvt. Ltd.
- Nishu Kohli
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING
- Publication number 20180025787
- Publication date Jan 25, 2018
- STMicroelectronics International N.V.
- Nishu Kohli
- G01 - MEASURING TESTING
Information Patent Application
AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING
- Publication number 20150179282
- Publication date Jun 25, 2015
- STMicroelectronics International N.V
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY
- Publication number 20150055400
- Publication date Feb 26, 2015
- STMicroelectronics International N.V
- NISHU KOHLI
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY
- Publication number 20150029795
- Publication date Jan 29, 2015
- STMicroelectronics International N.V
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL CLOCK EDGE TRIGGERED MEMORY
- Publication number 20140241102
- Publication date Aug 28, 2014
- STMicroelectronics International N.V
- Nishu KOHLI
- G11 - INFORMATION STORAGE
Information Patent Application
READ SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY
- Publication number 20130308397
- Publication date Nov 21, 2013
- STMICROELECTRONICS PVT. LTD.
- Nishu KOHLI
- G11 - INFORMATION STORAGE
Information Patent Application
WRITE SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY
- Publication number 20130308399
- Publication date Nov 21, 2013
- STMICROELECTRONICS PVT. LTD.
- Nishu KOHLI
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL PORT REGISTER FILE MEMORY CELL WITH REDUCED SUSCEPTIBILITY TO...
- Publication number 20130170288
- Publication date Jul 4, 2013
- STMICROELECTRONICS PVT. LTD.
- Nishu KOHLI
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL CLOCK EDGE TRIGGERED MEMORY
- Publication number 20130142003
- Publication date Jun 6, 2013
- STMicroelectronics, S.A.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Application
XY TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) CELL AND ARRAY
- Publication number 20130135914
- Publication date May 30, 2013
- STMICROELECTRONICS PVT. LTD.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Application
AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING
- Publication number 20130007548
- Publication date Jan 3, 2013
- STMICROELECTRONICS PVT. LTD.
- Nishu KOHLI
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF-TIMED MEMORY
- Publication number 20120170393
- Publication date Jul 5, 2012
- STMICROELECTRONICS PVT. LTD.
- Nishu Kohli
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY
- Publication number 20070201287
- Publication date Aug 30, 2007
- STMicroelectronics Pvt. Ltd.
- Nishu Kohli
- G11 - INFORMATION STORAGE

Nishu Kohli

Person

Patents Grantslast 30 patents

Automatic test-pattern generation for memory-shadow-logic testing

Automatic test-pattern generation for memory-shadow-logic testing

Selective dual cycle write operation for a self-timed memory

Programmable delay introducing circuit in self timed memory

Automatic test-pattern generation for memory-shadow-logic testing

Programmable delay introducing circuit in self-timed memory

XY ternary content addressable memory (TCAM) cell and array

Dual clock edge triggered memory

Read self timing circuitry for self-timed memory

Write self timing circuitry for self-timed memory

Dual clock edge triggered memory

Dual port register file memory cell with reduced susceptibility to...

Programmable delay introducing circuit in self timed memory

Patents Applicationslast 30 patents

AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING

AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING

PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY

SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY

DUAL CLOCK EDGE TRIGGERED MEMORY

READ SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY

WRITE SELF TIMING CIRCUITRY FOR SELF-TIMED MEMORY

DUAL PORT REGISTER FILE MEMORY CELL WITH REDUCED SUSCEPTIBILITY TO...

DUAL CLOCK EDGE TRIGGERED MEMORY

XY TERNARY CONTENT ADDRESSABLE MEMORY (TCAM) CELL AND ARRAY

AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING

PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF-TIMED MEMORY

PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY