Nitesh KUMAR

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gate-all-around integrated circuit structures having fin stack isol...
- Patent number 11,594,637
- Issue date Feb 28, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
DEPOP using cyclic selective spacer etch
- Patent number 11,569,370
- Issue date Jan 31, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS
- Publication number 20230420528
- Publication date Dec 28, 2023
- Intel Corporation
- Nitesh Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE AND DRAIN CONTACTS FORMED USING SACRIFICIAL REGIONS OF SOURC...
- Publication number 20230402513
- Publication date Dec 14, 2023
- Intel Corporation
- Rohit Galatage
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE REMOVAL OF CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA...
- Publication number 20230395678
- Publication date Dec 7, 2023
- Intel Corporation
- Munzarin F. Qayyum
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D SOURCE AND DRAIN CONTACTS TUNED FOR VERTICALLY STACKED PMOS AND...
- Publication number 20230395718
- Publication date Dec 7, 2023
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D SOURCE AND DRAIN CONTACTS TUNED FOR PMOS AND NMOS
- Publication number 20230395717
- Publication date Dec 7, 2023
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAI...
- Publication number 20230207651
- Publication date Jun 29, 2023
- Mohammad HASAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF CAVITY SPACER AND SOURCE-DRAIN EPITAXIAL GROWTH FOR SC...
- Publication number 20230197818
- Publication date Jun 22, 2023
- Intel Corporation
- Nitesh Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAI...
- Publication number 20230197855
- Publication date Jun 22, 2023
- Mohammad HASAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TRANSISTORS WITH REMOVED EPI BARRIER
- Publication number 20230187509
- Publication date Jun 15, 2023
- Intel Corporation
- Urusa Alaan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...
- Publication number 20230163215
- Publication date May 25, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING GATE HEIGHT RE...
- Publication number 20220416042
- Publication date Dec 29, 2022
- Intel Corporation
- William HSU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LATERAL CONFINEMENT OF SOURCE DRAIN EPITAXIAL GROWTH IN NON-PLANAR...
- Publication number 20220416044
- Publication date Dec 29, 2022
- Intel Corporation
- Nitesh KUMAR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANORIBBON SUBFIN ISOLATION BY BACKSIDE SILICON SUBSTRATE REMOVAL W...
- Publication number 20220416041
- Publication date Dec 29, 2022
- Intel Corporation
- Mohammad HASAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...
- Publication number 20210305430
- Publication date Sep 30, 2021
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEPOP USING CYCLIC SELECTIVE SPACER ETCH
- Publication number 20200411661
- Publication date Dec 31, 2020
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS

Nitesh KUMAR

Person

Patents Grantslast 30 patents

Gate-all-around integrated circuit structures having fin stack isol...

DEPOP using cyclic selective spacer etch

Patents Applicationslast 30 patents

SELF-ALIGNED EMBEDDED SOURCE AND DRAIN CONTACTS

SOURCE AND DRAIN CONTACTS FORMED USING SACRIFICIAL REGIONS OF SOURC...

SELECTIVE REMOVAL OF CHANNEL BODIES IN STACKED GATE-ALL-AROUND (GAA...

3D SOURCE AND DRAIN CONTACTS TUNED FOR VERTICALLY STACKED PMOS AND...

3D SOURCE AND DRAIN CONTACTS TUNED FOR PMOS AND NMOS

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAI...

FORMATION OF CAVITY SPACER AND SOURCE-DRAIN EPITAXIAL GROWTH FOR SC...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING SOURCE OR DRAI...

STACKED TRANSISTORS WITH REMOVED EPI BARRIER

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING GATE HEIGHT RE...

LATERAL CONFINEMENT OF SOURCE DRAIN EPITAXIAL GROWTH IN NON-PLANAR...

NANORIBBON SUBFIN ISOLATION BY BACKSIDE SILICON SUBSTRATE REMOVAL W...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...

DEPOP USING CYCLIC SELECTIVE SPACER ETCH