Nitin D. Godiwala

Person

Costa Mesa, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and an apparatus for work request arbitration in a network p...
- Patent number 9,838,471
- Issue date Dec 5, 2017
- Cavium, Inc.
- Wilson Parkhurst Snyder
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and an apparatus for pre-fetching and processing work for pr...
- Patent number 9,811,467
- Issue date Nov 7, 2017
- Cavium, Inc.
- Wilson Parkhurst Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for arbitration for virtual channels to prevent l...
- Patent number 7,773,617
- Issue date Aug 10, 2010
- SiCortex, Inc.
- Nitin Godiwala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for communicating on a richly connected multi-pro...
- Patent number 7,773,616
- Issue date Aug 10, 2010
- SiCortex, Inc.
- Matthew H. Reilly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for preventing deadlock in richly-connected multi...
- Patent number 7,773,618
- Issue date Aug 10, 2010
- SiCortex, Inc.
- Judson S. Leonard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mesochronous clock system and method to minimize latency and buffer...
- Patent number 7,689,856
- Issue date Mar 30, 2010
- SiCortex, Inc.
- Nitin Godiwala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for scheduling message transmission and processin...
- Patent number 7,295,557
- Issue date Nov 13, 2007
- Emulex Design & Manufacturing Corporation
- Shawn A. Clayton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for regulating message flow in a digital data net...
- Patent number 7,283,471
- Issue date Oct 16, 2007
- Emulex Design & Manufacturing Corporation
- Maria C. Gutierrez
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for scheduling message transmission and processin...
- Patent number 6,795,442
- Issue date Sep 21, 2004
- Emulex Design & Manufacturing Corporation
- Shawn A. Clayton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Distributed switch and connection control arrangement and method fo...
- Patent number 6,791,948
- Issue date Sep 14, 2004
- Emulex Corporation
- Peter J. Desnoyers
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for regulating message flow in a digital data net...
- Patent number 6,570,850
- Issue date May 27, 2003
- Giganet, Inc.
- Maria C. Gutierrez
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Bus interface slicing mechanism allowing for a control/data path slice
- Patent number 6,077,306
- Issue date Jun 20, 2000
- Compaq Computer Corporation
- Jeffrey A. Metzger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bus interface slicing mechanism allowing for a control/data-path slice
- Patent number 5,918,029
- Issue date Jun 29, 1999
- Digital Equipment Corporation
- Jeffrey A. Metzger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test methodology for exceeding tester pin count for an asic device
- Patent number 5,712,858
- Issue date Jan 27, 1998
- Digital Equipment Corporation
- Nitin Dhiroobhai Godiwala
- G01 - MEASURING TESTING
Information Patent Grant
Fault management scheme for a cache memory
- Patent number 5,629,950
- Issue date May 13, 1997
- Digital Equipment Corporation
- Nitin D. Godiwala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent snoopy bus arbiter
- Patent number 5,555,382
- Issue date Sep 10, 1996
- Digital Equipment Corporation
- Kurt M. Thaller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for forming an exchange address for a system w...
- Patent number 5,553,258
- Issue date Sep 3, 1996
- Digital Equipment Corporation
- Nitin D. Godiwala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheme for error handling in a computer system
- Patent number 5,361,267
- Issue date Nov 1, 1994
- Digital Equipment Corporation
- Nitin D. Godiwala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Duplicate tag store for a processor having primary and backup cache...
- Patent number 5,319,766
- Issue date Jun 7, 1994
- Digital Equipment Corporation
- Kurt M. Thaller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aborting synchronizer
- Patent number 5,305,354
- Issue date Apr 19, 1994
- Digital Equipment Corporation
- Kurt M Thaller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multisignal synchronizer with shared last stage
- Patent number 5,274,628
- Issue date Dec 28, 1993
- Digital Equipment Corporation
- Kurt M. Thaller
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND AN APPARATUS FOR WORK REQUEST ARBITRATION IN A NETWORK P...
- Publication number 20150222698
- Publication date Aug 6, 2015
- Cavium, Inc.
- Wilson Parkhurst Snyder
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND AN APPARATUS FOR PRE-FETCHING AND PROCESSING WORK FOR PR...
- Publication number 20150220360
- Publication date Aug 6, 2015
- Cavium, Inc.
- Wilson Parkhurst Snyder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Mesochronous clock system and method to minimize latency and buffer...
- Publication number 20080109671
- Publication date May 8, 2008
- SiCortex, Inc.
- Nitin Godiwala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for preventing deadlock in richly-connected multi...
- Publication number 20080107106
- Publication date May 8, 2008
- SiCortex, Inc.
- Judson S. Leonard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for arbitration for virtual channels to prevent l...
- Publication number 20080109586
- Publication date May 8, 2008
- SiCortex, Inc.
- Nitin Godiwala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Large scale multi-processor system with a link-level interconnect p...
- Publication number 20080107116
- Publication date May 8, 2008
- SiCortex, Inc.
- Nitin Godiwala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Large scale computing system with multi-lane mesochronous data tran...
- Publication number 20080109672
- Publication date May 8, 2008
- SiCortex, Inc.
- Nitin Godiwala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for communicating on a richly connected multi-pro...
- Publication number 20080107105
- Publication date May 8, 2008
- SiCortex, Inc.
- Matthew H. Reilly
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for scheduling message transmission and processin...
- Publication number 20040208181
- Publication date Oct 21, 2004
- Emulex Design & Manufacturing Corporation
- Shawn A. Clayton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for regulating message flow in a digital data net...
- Publication number 20030174647
- Publication date Sep 18, 2003
- Emulex Corporation, a California corporation
- Maria C. Gutierrez
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Nitin D. Godiwala

Person

Patents Grantslast 30 patents

Method and an apparatus for work request arbitration in a network p...

Method and an apparatus for pre-fetching and processing work for pr...

System and method for arbitration for virtual channels to prevent l...

System and method for communicating on a richly connected multi-pro...

System and method for preventing deadlock in richly-connected multi...

Mesochronous clock system and method to minimize latency and buffer...

System and method for scheduling message transmission and processin...

System and method for regulating message flow in a digital data net...

System and method for scheduling message transmission and processin...

Distributed switch and connection control arrangement and method fo...

System and method for regulating message flow in a digital data net...

Bus interface slicing mechanism allowing for a control/data path slice

Bus interface slicing mechanism allowing for a control/data-path slice

Test methodology for exceeding tester pin count for an asic device

Fault management scheme for a cache memory

Intelligent snoopy bus arbiter

Method and apparatus for forming an exchange address for a system w...

Scheme for error handling in a computer system

Duplicate tag store for a processor having primary and backup cache...

Aborting synchronizer

Multisignal synchronizer with shared last stage

Patents Applicationslast 30 patents

METHOD AND AN APPARATUS FOR WORK REQUEST ARBITRATION IN A NETWORK P...

METHOD AND AN APPARATUS FOR PRE-FETCHING AND PROCESSING WORK FOR PR...

Mesochronous clock system and method to minimize latency and buffer...

System and method for preventing deadlock in richly-connected multi...

System and method for arbitration for virtual channels to prevent l...

Large scale multi-processor system with a link-level interconnect p...

Large scale computing system with multi-lane mesochronous data tran...

System and method for communicating on a richly connected multi-pro...

System and method for scheduling message transmission and processin...

System and method for regulating message flow in a digital data net...