Nitin Mohan

Person

Northborough, MA, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for performing a failure assessment of an integra...
- Patent number 11,669,419
- Issue date Jun 6, 2023
- Marvell Asia Pte, Ltd.
- Zahi Abuhamdeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DLL-based clocking architecture with programmable delay at phase de...
- Patent number 11,545,981
- Issue date Jan 3, 2023
- Marvell Asia Pte, Ltd.
- Thucydides Xanthopoulos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Traversing a variable delay line in a deterministic number of clock...
- Patent number 11,545,987
- Issue date Jan 3, 2023
- Marvell Asia Pte, Ltd.
- Nitin Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Droop detection and mitigation
- Patent number 11,402,413
- Issue date Aug 2, 2022
- Marvell Asia Pte, Ltd.
- Nitin Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clocking architecture for DVFS with low-frequency DLL locking
- Patent number 10,784,871
- Issue date Sep 22, 2020
- Marvell Asia Pte, Ltd.
- Thucydides Xanthopoulos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Glitch-free PLL Multiplexer
- Patent number 10,530,370
- Issue date Jan 7, 2020
- Marvell International Ltd.
- Nitin Mohan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance shifter circuit
- Patent number 9,904,511
- Issue date Feb 27, 2018
- Cavium, Inc.
- Nitin Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to measure edge-rate timing penalty of digital integrated ci...
- Patent number 9,740,807
- Issue date Aug 22, 2017
- Cavium, Inc.
- Nitin Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder decoder
- Patent number 9,645,790
- Issue date May 9, 2017
- Cavium, Inc.
- Edward Beckman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplexer flop
- Patent number 9,130,549
- Issue date Sep 8, 2015
- Cavium, Inc.
- Suresh Balasubramanian
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
HIGH PERFORMANCE SHIFTER CIRCUIT
- Publication number 20160139879
- Publication date May 19, 2016
- Cavium, Inc.
- Nitin Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO MEASURE EDGE-RATE TIMING PENALTY OF DIGITAL INTEGRATED CI...
- Publication number 20160140272
- Publication date May 19, 2016
- Cavium, Inc.
- Nitin Mohan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDER DECODER
- Publication number 20160132294
- Publication date May 12, 2016
- Cavium, Inc.
- Edward Beckman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLEXER FLOP
- Publication number 20150061741
- Publication date Mar 5, 2015
- Cavium, Inc.
- Suresh Balasubramanian
- H03 - BASIC ELECTRONIC CIRCUITRY

Nitin Mohan

Person

Patents Grantslast 30 patents

System and method for performing a failure assessment of an integra...

DLL-based clocking architecture with programmable delay at phase de...

Traversing a variable delay line in a deterministic number of clock...

Droop detection and mitigation

Clocking architecture for DVFS with low-frequency DLL locking

Glitch-free PLL Multiplexer

High performance shifter circuit

Method to measure edge-rate timing penalty of digital integrated ci...

Adder decoder

Multiplexer flop

Patents Applicationslast 30 patents

HIGH PERFORMANCE SHIFTER CIRCUIT

METHOD TO MEASURE EDGE-RATE TIMING PENALTY OF DIGITAL INTEGRATED CI...

ADDER DECODER

MULTIPLEXER FLOP