Nobuo Kojima

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
4 to 2 adder
- Patent number 6,584,485
- Issue date Jun 24, 2003
- International Business Machines Corporation
- Naoaki Aoki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
5-to-2 binary adder
- Patent number 6,578,063
- Issue date Jun 10, 2003
- International Business Machines Corporation
- Nobuo Kojima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor cycle time independent pipeline cache and method for pipe...
- Patent number 6,453,390
- Issue date Sep 17, 2002
- International Business Machines Corporation
- Naoaki Aoki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Edge-triggered latch with balanced pass-transistor logic trigger
- Patent number 6,445,217
- Issue date Sep 3, 2002
- International Business Machines Corporation
- Nobuo Kojima
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Edge-triggered latch with symmetric complementary pass-transistor l...
- Patent number 6,437,624
- Issue date Aug 20, 2002
- International Business Machines Corporation
- Nobuo Kojima
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Set-associative cache memory having a built-in set prediction array
- Patent number 6,356,990
- Issue date Mar 12, 2002
- International Business Machines Corporation
- Naoaki Aoki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating true/complement signals
- Patent number 6,239,620
- Issue date May 29, 2001
- International Business Machines Corporation
- Naoaki Aoki
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
EDGE-TRIGGERED LATCH WITH BALANCED PASS-TRANSISTOR LOGIC TRIGGER
- Publication number 20020130693
- Publication date Sep 19, 2002
- International Business Machines Corporation
- Nobuo Kojima
- H03 - BASIC ELECTRONIC CIRCUITRY

Nobuo Kojima

Person

Patents Grantslast 30 patents

4 to 2 adder

5-to-2 binary adder

Processor cycle time independent pipeline cache and method for pipe...

Edge-triggered latch with balanced pass-transistor logic trigger

Edge-triggered latch with symmetric complementary pass-transistor l...

Set-associative cache memory having a built-in set prediction array

Method and apparatus for generating true/complement signals

Patents Applicationslast 30 patents

EDGE-TRIGGERED LATCH WITH BALANCED PASS-TRANSISTOR LOGIC TRIGGER