Nobuyuki Takagi

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Kanagawa-ken, JP

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Patents Grantslast 30 patents

Information Patent Grant
Dual-loop PLL circuit and chrominance demodulation circuit
- Patent number 6,522,366
- Issue date Feb 18, 2003
- Fujitsu General Limited
- Junichi Onodera
- H04 - ELECTRIC COMMUNICATION TECHNIQUE