Noriyuki Ito

Person

Kawasaki, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Delay analysis device, delay analysis method, and delay analysis pr...
- Patent number 8,407,021
- Issue date Mar 26, 2013
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packaging design supporting device and packaging design supporting...
- Patent number 8,341,583
- Issue date Dec 25, 2012
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit device operating frequency determi...
- Patent number 7,855,572
- Issue date Dec 21, 2010
- Fujitsu Limited
- Noriyuki Ito
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit designing device, integrated circuit designing m...
- Patent number 7,757,192
- Issue date Jul 13, 2010
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for designing integrated circuit
- Patent number 7,757,188
- Issue date Jul 13, 2010
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for analyzing delay defect
- Patent number 7,617,431
- Issue date Nov 10, 2009
- Fujitsu Limited
- Noriyuki Ito
- G01 - MEASURING TESTING
Information Patent Grant
Layout evaluating apparatus
- Patent number 7,559,042
- Issue date Jul 7, 2009
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design support apparatus, design support program and design support...
- Patent number 7,328,422
- Issue date Feb 5, 2008
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Steiner tree handling device, Steiner tree handling method, and Ste...
- Patent number 7,266,799
- Issue date Sep 4, 2007
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement/net wiring processing system
- Patent number 7,240,317
- Issue date Jul 3, 2007
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement/net wiring processing system
- Patent number 7,240,318
- Issue date Jul 3, 2007
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic circuit design method, simulation apparatus and computer...
- Patent number 7,086,018
- Issue date Aug 1, 2006
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design data processing method and recording medium
- Patent number 6,874,137
- Issue date Mar 29, 2005
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing budget designing method
- Patent number 6,684,374
- Issue date Jan 27, 2004
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement/net wiring processing system
- Patent number 6,629,305
- Issue date Sep 30, 2003
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interactive circuit designing apparatus which displays a result of...
- Patent number 6,240,541
- Issue date May 29, 2001
- Fujitsu Limited
- Mitsuru Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wire processing method, wire processing equipment, and recording me...
- Patent number 6,223,328
- Issue date Apr 24, 2001
- Fujitsu, Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock routing design method using a hieraichical layout design
- Patent number 5,889,682
- Issue date Mar 30, 1999
- Fujitsu Limited
- Masayuki Omura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit designing apparatus of an interactive type
- Patent number 5,889,677
- Issue date Mar 30, 1999
- Fujitsu Limited
- Mitsuru Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interactive circuit designing apparatus
- Patent number 5,787,268
- Issue date Jul 28, 1998
- Fujitsu Limited
- Yaroku Sugiyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation system for an additional circuit provided in a...
- Patent number 5,610,830
- Issue date Mar 11, 1997
- Fujitsu Limited
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DELAY ANALYSIS DEVICE, DELAY ANALYSIS METHOD, AND DELAY ANALYSIS PR...
- Publication number 20110082657
- Publication date Apr 7, 2011
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay Test Apparatus, Delay Test Method and Delay Test Program
- Publication number 20110077893
- Publication date Mar 31, 2011
- Fujitsu Limited
- Noriyuki Ito
- G01 - MEASURING TESTING
Information Patent Application
Packaging design supporting device and packaging design supporting...
- Publication number 20100199248
- Publication date Aug 5, 2010
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit device operating frequency determi...
- Publication number 20100194422
- Publication date Aug 5, 2010
- FUJITSU LIMITED
- Noriyuki Ito
- G01 - MEASURING TESTING
Information Patent Application
Timing analysis apparatus and timing analysis method
- Publication number 20100095261
- Publication date Apr 15, 2010
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGNING DEVICE, INTEGRATED CIRCUIT DESIGNING M...
- Publication number 20080184179
- Publication date Jul 31, 2008
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for designing integrated circuit
- Publication number 20080086711
- Publication date Apr 10, 2008
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for analyzing delay defect
- Publication number 20080072108
- Publication date Mar 20, 2008
- FUJITSU LIMITED
- Noriyuki Ito
- G01 - MEASURING TESTING
Information Patent Application
LAYOUT EVALUATING APPARATUS
- Publication number 20080022238
- Publication date Jan 24, 2008
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design support apparatus, design support program and design support...
- Publication number 20060112365
- Publication date May 25, 2006
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Steiner tree handling device, steiner tree handling method, and ste...
- Publication number 20050229137
- Publication date Oct 13, 2005
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement/net wiring processing system
- Publication number 20040153988
- Publication date Aug 5, 2004
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement/net wiring processing system
- Publication number 20040148582
- Publication date Jul 29, 2004
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Electronic circuit design method, simulation apparatus and computer...
- Publication number 20030237066
- Publication date Dec 25, 2003
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing budget designing method
- Publication number 20030014720
- Publication date Jan 16, 2003
- FUJITSU LIMITED
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement/net wiring processing system
- Publication number 20020042904
- Publication date Apr 11, 2002
- Noriyuki Ito
- G06 - COMPUTING CALCULATING COUNTING

Noriyuki Ito

Person

Patents Grantslast 30 patents

Delay analysis device, delay analysis method, and delay analysis pr...

Packaging design supporting device and packaging design supporting...

Semiconductor integrated circuit device operating frequency determi...

Integrated circuit designing device, integrated circuit designing m...

Method and apparatus for designing integrated circuit

Method and apparatus for analyzing delay defect

Layout evaluating apparatus

Design support apparatus, design support program and design support...

Steiner tree handling device, Steiner tree handling method, and Ste...

Placement/net wiring processing system

Placement/net wiring processing system

Electronic circuit design method, simulation apparatus and computer...

Design data processing method and recording medium

Timing budget designing method

Placement/net wiring processing system

Interactive circuit designing apparatus which displays a result of...

Wire processing method, wire processing equipment, and recording me...

Clock routing design method using a hieraichical layout design

Circuit designing apparatus of an interactive type

Interactive circuit designing apparatus

Automatic generation system for an additional circuit provided in a...

Patents Applicationslast 30 patents

DELAY ANALYSIS DEVICE, DELAY ANALYSIS METHOD, AND DELAY ANALYSIS PR...

Delay Test Apparatus, Delay Test Method and Delay Test Program

Packaging design supporting device and packaging design supporting...

Semiconductor integrated circuit device operating frequency determi...

Timing analysis apparatus and timing analysis method

INTEGRATED CIRCUIT DESIGNING DEVICE, INTEGRATED CIRCUIT DESIGNING M...

Method and apparatus for designing integrated circuit

Method and apparatus for analyzing delay defect

LAYOUT EVALUATING APPARATUS

Design support apparatus, design support program and design support...

Steiner tree handling device, steiner tree handling method, and ste...

Placement/net wiring processing system

Placement/net wiring processing system

Electronic circuit design method, simulation apparatus and computer...

Timing budget designing method

Placement/net wiring processing system