Norman Card

Person

Vestal, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Systems and methods for scan chain stitching
- Patent number 12,007,440
- Issue date Jun 11, 2024
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation event reduction and power control during MBIST through c...
- Patent number 10,783,299
- Issue date Sep 22, 2020
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method and computer-accessible medium for automated identif...
- Patent number 10,699,795
- Issue date Jun 30, 2020
- Cadence Design Systems, Inc.
- Norman Card
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Failing read count diagnostics for memory built-in self-test
- Patent number 10,593,419
- Issue date Mar 17, 2020
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
On demand data stream controller for programming and executing oper...
- Patent number 10,541,043
- Issue date Jan 21, 2020
- Cadence Design Systems, Inc.
- Carl Alexander Wisnesky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-channel, programmable fuse control unit
- Patent number 10,504,607
- Issue date Dec 10, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic diagnostics analysis for memory built-in self-test
- Patent number 10,482,989
- Issue date Nov 19, 2019
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Register-transfer level design engineering change order strategy
- Patent number 10,395,747
- Issue date Aug 27, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and computer-readable media utilizing improved da...
- Patent number 10,387,599
- Issue date Aug 20, 2019
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying results in simulation through simulation add-on to suppor...
- Patent number 10,387,598
- Issue date Aug 20, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Customizable built-in self-test testplans for memory units
- Patent number 10,319,459
- Issue date Jun 11, 2019
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory built-in self-test logic in an integrated circuit design
- Patent number 10,095,822
- Issue date Oct 9, 2018
- Cadence Design Systems, Inc.
- Navneet Kaushik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated method identifying physical memories within a core or mac...
- Patent number 10,007,489
- Issue date Jun 26, 2018
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for testing error correction code (ECC) logic...
- Patent number 9,865,362
- Issue date Jan 9, 2018
- Cadence Design Systems, Inc.
- Puneet Arora
- G11 - INFORMATION STORAGE
Information Patent Grant
Power domain aware insertion methods and designs for testing and re...
- Patent number 9,640,280
- Issue date May 2, 2017
- Cadence Design Systems, Inc.
- Puneet Arora
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for optimizing memory-built-in-self test
- Patent number 8,990,749
- Issue date Mar 24, 2015
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing memory-built-in-self test
- Patent number 8,719,761
- Issue date May 6, 2014
- Candence Design Systems, Inc.
- Norman Card
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low cost production testing for memory
- Patent number 8,677,196
- Issue date Mar 18, 2014
- Cadence Design Systems, Inc.
- Steven Lee Gregor
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for Optimizing Memory-Built-In-Self Test
- Publication number 20140089874
- Publication date Mar 27, 2014
- Cadence Design Systems, Inc.
- Norman Card
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Optimizing Memory-Built-In-Self Test
- Publication number 20140089875
- Publication date Mar 27, 2014
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING

Norman Card

Person

Patents Grantslast 30 patents

Systems and methods for scan chain stitching

Simulation event reduction and power control during MBIST through c...

System, method and computer-accessible medium for automated identif...

Failing read count diagnostics for memory built-in self-test

On demand data stream controller for programming and executing oper...

Multiple-channel, programmable fuse control unit

Dynamic diagnostics analysis for memory built-in self-test

Register-transfer level design engineering change order strategy

Systems, methods, and computer-readable media utilizing improved da...

Verifying results in simulation through simulation add-on to suppor...

Customizable built-in self-test testplans for memory units

Memory built-in self-test logic in an integrated circuit design

Automated method identifying physical memories within a core or mac...

Method and apparatus for testing error correction code (ECC) logic...

Power domain aware insertion methods and designs for testing and re...

Method and apparatus for optimizing memory-built-in-self test

Method and apparatus for optimizing memory-built-in-self test

Low cost production testing for memory

Patents Applicationslast 30 patents

Method and Apparatus for Optimizing Memory-Built-In-Self Test

Method and Apparatus for Optimizing Memory-Built-In-Self Test