Nui Chong

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Single event upset tolerant memory device
- Patent number 12,045,469
- Issue date Jul 23, 2024
- Xilinx, Inc.
- Kumar Rahul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wafer testing and structures for wafer testing
- Patent number 11,650,249
- Issue date May 16, 2023
- Xilinx, Inc.
- Yan Wang
- G01 - MEASURING TESTING
Information Patent Grant
Runtime measurement of process variations and supply voltage charac...
- Patent number 11,585,854
- Issue date Feb 21, 2023
- Xilinx, Inc.
- Da Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Warpage reduction
- Patent number 11,164,749
- Issue date Nov 2, 2021
- Xilinx, Inc.
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Testing of bonded wafers and structures for testing bonded wafers
- Patent number 11,119,146
- Issue date Sep 14, 2021
- Xilinx, Inc.
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC die with dummy structures
- Patent number 11,114,344
- Issue date Sep 7, 2021
- Xilinx, Inc.
- Hui-Wen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test circuits for testing a die stack
- Patent number 11,054,461
- Issue date Jul 6, 2021
- Xilinx, Inc.
- Nui Chong
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit skew determination
- Patent number 10,756,711
- Issue date Aug 25, 2020
- Xilinx, Inc.
- Amitava Majumdar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Chip package assembly with modular core dice
- Patent number 10,692,837
- Issue date Jun 23, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit die with in-chip heat sink
- Patent number 10,629,512
- Issue date Apr 21, 2020
- Xilinx, Inc.
- Hong-Tsz Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectively disconnecting a memory cell from a power supply
- Patent number 10,566,050
- Issue date Feb 18, 2020
- Xilinx, Inc.
- Shidong Zhou
- G11 - INFORMATION STORAGE
Information Patent Grant
In-die transistor characterization in an IC
- Patent number 10,379,155
- Issue date Aug 13, 2019
- Xilinx, Inc.
- Ping-Chin Yeh
- G01 - MEASURING TESTING
Information Patent Grant
Method and design of low sheet resistance MEOL resistors
- Patent number 10,103,139
- Issue date Oct 16, 2018
- Xilinx, Inc.
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using an integrated circuit die for multiple devices
- Patent number 10,043,724
- Issue date Aug 7, 2018
- Xilinx, Inc.
- Brian C. Gaide
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two gate pitch FPGA memory cell
- Patent number 9,177,634
- Issue date Nov 3, 2015
- Xilinx, Inc.
- Steven P. Young
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for electrostatic discharge protection
- Patent number 8,194,372
- Issue date Jun 5, 2012
- Xilinx, Inc.
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Embedded inductor
- Patent number 8,068,004
- Issue date Nov 29, 2011
- Xilinx, Inc.
- Nui Chong
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method and apparatus for compensating an integrated circuit layout...
- Patent number 7,673,270
- Issue date Mar 2, 2010
- Xilinx, Inc.
- Yan Wang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
High-voltage protection device and process
- Patent number 7,307,319
- Issue date Dec 11, 2007
- Lattice Semiconductor Corporation
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge simulation
- Patent number 7,024,646
- Issue date Apr 4, 2006
- Lattice Semiconductor Corporation
- Stewart Logie
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SINGLE EVENT UPSET TOLERANT MEMORY DEVICE
- Publication number 20240201863
- Publication date Jun 20, 2024
- Xilinx, Inc.
- Kumar RAHUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF TESTING STRUCTURES AND STACKING WAFERS
- Publication number 20230317529
- Publication date Oct 5, 2023
- Xilinx, Inc.
- Yan WANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DIE WITH IN-CHIP HEAT SINK
- Publication number 20200006186
- Publication date Jan 2, 2020
- Xilinx, Inc.
- Hong-Tsz Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS
- Publication number 20170012041
- Publication date Jan 12, 2017
- Xilinx, Inc.
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC
- Publication number 20160097805
- Publication date Apr 7, 2016
- Xilinx, Inc.
- Ping-Chin Yeh
- G01 - MEASURING TESTING
Information Patent Application
Metal junction diode and process
- Publication number 20060157748
- Publication date Jul 20, 2006
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Diode with low junction capacitance
- Publication number 20060125014
- Publication date Jun 15, 2006
- Nui Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrostatic discharge protection circuits
- Publication number 20050213271
- Publication date Sep 29, 2005
- Nui Chong
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Electrostatic discharge simulation
- Publication number 20050172246
- Publication date Aug 4, 2005
- Stewart Logie
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Single event upset tolerant memory device

Wafer testing and structures for wafer testing

Runtime measurement of process variations and supply voltage charac...

Warpage reduction

Testing of bonded wafers and structures for testing bonded wafers

IC die with dummy structures

Test circuits for testing a die stack

Integrated circuit skew determination

Chip package assembly with modular core dice

Integrated circuit die with in-chip heat sink

Selectively disconnecting a memory cell from a power supply

In-die transistor characterization in an IC

Method and design of low sheet resistance MEOL resistors

Using an integrated circuit die for multiple devices

Two gate pitch FPGA memory cell

Systems and methods for electrostatic discharge protection

Embedded inductor

Method and apparatus for compensating an integrated circuit layout...

High-voltage protection device and process

Electrostatic discharge simulation

Patents Applicationslast 30 patents

SINGLE EVENT UPSET TOLERANT MEMORY DEVICE

METHOD OF TESTING STRUCTURES AND STACKING WAFERS

INTEGRATED CIRCUIT DIE WITH IN-CHIP HEAT SINK

METHOD AND DESIGN OF LOW SHEET RESISTANCE MEOL RESISTORS

IN-DIE TRANSISTOR CHARACTERIZATION IN AN IC

Metal junction diode and process

Diode with low junction capacitance

Electrostatic discharge protection circuits

Electrostatic discharge simulation