Nur Engin

Person

Eindhoven, NL

People

Patents Grantslast 30 patents

Information Patent Grant
Signal processing with error correction
- Patent number 10,644,837
- Issue date May 5, 2020
- NXP B.V.
- Semih Serbetli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit device and method for reading data from an SRAM...
- Patent number 10,437,666
- Issue date Oct 8, 2019
- NXP B.V.
- Nur Engin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device and method for applying error correction...
- Patent number 10,223,197
- Issue date Mar 5, 2019
- NXP B.V.
- Ajay Kapoor
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for dynamically assigning master/slave roles w...
- Patent number 10,171,223
- Issue date Jan 1, 2019
- NXP B.V.
- Artur Tadeusz Burchard
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Demodulation and decoding
- Patent number 10,097,382
- Issue date Oct 9, 2018
- NXP B.V.
- Semih Serbetli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Signal processing circuits
- Patent number 9,893,920
- Issue date Feb 13, 2018
- NXP B.V.
- Nur Engin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated circuit device and method for reducing SRAM leakage
- Patent number 9,778,983
- Issue date Oct 3, 2017
- NXP B.V.
- Nur Engin
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced memory iterative baseband processing
- Patent number 9,425,922
- Issue date Aug 23, 2016
- NXP B.V.
- Nur Engin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multi-standard viterbi processor
- Patent number 8,904,266
- Issue date Dec 2, 2014
- NXP, B.V.
- Weihua Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reconfigurable interleaver having reconfigurable counters
- Patent number 8,874,858
- Issue date Oct 28, 2014
- NXP, B.V.
- Nur Engin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scalar/vector processor that includes a functional unit with a vect...
- Patent number 8,510,534
- Issue date Aug 13, 2013
- ST-Ericsson SA
- Cornelis Hermanus Van Berkel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
N-way parallel turbo decoder architecture
- Patent number 8,438,434
- Issue date May 7, 2013
- NXP B.V.
- Nur Engin
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitwise reliability indicators from survivor bits in Viterbi decoders
- Patent number 8,433,975
- Issue date Apr 30, 2013
- NXP B.V.
- Andries Pieter Hekstra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
SIGNAL PROCESSING WITH ERROR CORRECTION
- Publication number 20200044775
- Publication date Feb 6, 2020
- NXP B.V.
- Semih Serbetli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY ASSIGNING MASTER/SLAVE ROLES W...
- Publication number 20180205508
- Publication date Jul 19, 2018
- NXP B.V.
- Artur Tadeusz BURCHARD
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DEMODULATION AND DECODING
- Publication number 20180176047
- Publication date Jun 21, 2018
- NXP B.V.
- Semih SERBETLI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SIGNAL PROCESSING CIRCUITS
- Publication number 20170288927
- Publication date Oct 5, 2017
- NXP B.V.
- Nur Engin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTEGRATED CIRCUIT DEVICE AND METHOD FOR READING DATA FROM AN SRAM...
- Publication number 20170039102
- Publication date Feb 9, 2017
- NXP B.V.
- Nur Engin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE AND METHOD FOR REDUCING SRAM LEAKAGE
- Publication number 20170039103
- Publication date Feb 9, 2017
- NXP B.V.
- Nur Engin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE AND METHOD FOR APPLYING ERROR CORRECTION...
- Publication number 20170039104
- Publication date Feb 9, 2017
- NXP B.V.
- Ajay Kapoor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reduced Memory Iterative Baseband Processing
- Publication number 20160050047
- Publication date Feb 18, 2016
- NXP, B.V.
- Nur Engin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS
- Publication number 20120042228
- Publication date Feb 16, 2012
- NXP B.V.
- Andries Pieter Hekstra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTI-STANDARD VITERBI PROCESSOR
- Publication number 20120042229
- Publication date Feb 16, 2012
- NXP B.V.
- Weihua Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RECONFIGURABLE INTERLEAVER HAVING RECONFIGURABLE COUNTERS
- Publication number 20110307673
- Publication date Dec 15, 2011
- NXP B.V.
- Nur Engin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
N-WAY PARALLEL TURBO DECODER ARCHITECTURE
- Publication number 20110161782
- Publication date Jun 30, 2011
- NXP B.V.
- Nur Engin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RECONFIGURABLE TURBO INTERLEAVERS FOR MULTIPLE STANDARDS
- Publication number 20110087949
- Publication date Apr 14, 2011
- NXP B.V.
- Angelo Raffaele Dilonardo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Loop control circuit for a data processor
- Publication number 20060107028
- Publication date May 18, 2006
- Koninklijke Philips Electronics N.V.
- Patrick Peter Elizabeth Meuwissen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalar/vector processor
- Publication number 20050240644
- Publication date Oct 27, 2005
- Cornelis Hermanus Van Berkel
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Signal processing with error correction

Integrated circuit device and method for reading data from an SRAM...

Integrated circuit device and method for applying error correction...

Method and apparatus for dynamically assigning master/slave roles w...

Demodulation and decoding

Signal processing circuits

Integrated circuit device and method for reducing SRAM leakage

Reduced memory iterative baseband processing

Multi-standard viterbi processor

Reconfigurable interleaver having reconfigurable counters

Scalar/vector processor that includes a functional unit with a vect...

N-way parallel turbo decoder architecture

Bitwise reliability indicators from survivor bits in Viterbi decoders

Patents Applicationslast 30 patents

SIGNAL PROCESSING WITH ERROR CORRECTION

METHOD AND APPARATUS FOR DYNAMICALLY ASSIGNING MASTER/SLAVE ROLES W...

DEMODULATION AND DECODING

SIGNAL PROCESSING CIRCUITS

INTEGRATED CIRCUIT DEVICE AND METHOD FOR READING DATA FROM AN SRAM...

INTEGRATED CIRCUIT DEVICE AND METHOD FOR REDUCING SRAM LEAKAGE

INTEGRATED CIRCUIT DEVICE AND METHOD FOR APPLYING ERROR CORRECTION...

Reduced Memory Iterative Baseband Processing

BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS

MULTI-STANDARD VITERBI PROCESSOR

RECONFIGURABLE INTERLEAVER HAVING RECONFIGURABLE COUNTERS

N-WAY PARALLEL TURBO DECODER ARCHITECTURE

RECONFIGURABLE TURBO INTERLEAVERS FOR MULTIPLE STANDARDS

Loop control circuit for a data processor

Scalar/vector processor