Oleg Levitsky

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method, system, and computer program product for implementing proto...
- Patent number 9,760,667
- Issue date Sep 12, 2017
- Cadence Design Systems, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine readable products for single pass parallel hierarchical tim...
- Patent number 9,165,098
- Issue date Oct 20, 2015
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-phase models for timing closure of integrated circuit designs
- Patent number 9,152,742
- Issue date Oct 6, 2015
- Cadence Design Systems, Inc.
- Dinesh Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for implementing full...
- Patent number 9,141,740
- Issue date Sep 22, 2015
- Cadence Design Systems, Inc.
- Dongzi Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for synchronous hiera...
- Patent number 9,053,270
- Issue date Jun 9, 2015
- Cadence Design Systems, Inc.
- Sushobhit Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing budgeting of nested partitions for hierarchical integrated c...
- Patent number 8,977,995
- Issue date Mar 10, 2015
- Cadence Design Systems, Inc.
- Sumit Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design system and method of generating hierarchical block-l...
- Patent number 8,977,994
- Issue date Mar 10, 2015
- Cadence Design Systems, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for single pass parallel hierarchical timing closure of int...
- Patent number 8,935,642
- Issue date Jan 13, 2015
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for synchronous hiera...
- Patent number 8,769,455
- Issue date Jul 1, 2014
- Cadence Design Systems, Inc.
- Sushobhit Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for generating a user interface for timing budget analysis...
- Patent number 8,745,560
- Issue date Jun 3, 2014
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing clock tree prototyping
- Patent number 8,719,743
- Issue date May 6, 2014
- Cadence Design Systems, Inc.
- Paul W. Kollaritsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-phase models for timing closure of integrated circuit designs
- Patent number 8,640,066
- Issue date Jan 28, 2014
- Cadence Design Systems, Inc.
- Dinesh Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common path pessimism removal for hierarchical timing analysis
- Patent number 8,572,532
- Issue date Oct 29, 2013
- Cadence Design Systems, Inc.
- Sushobhit Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems for single pass parallel hierarchical timing closure of int...
- Patent number 8,539,402
- Issue date Sep 17, 2013
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User interface for timing budget analysis of integrated circuit des...
- Patent number 8,504,978
- Issue date Aug 6, 2013
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow methodology for single pass parallel hierarchical timing closu...
- Patent number 8,365,113
- Issue date Jan 29, 2013
- Cadence Design Systems, Inc.
- Vivek Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of computing pin criticalities under process vari...
- Patent number 8,151,229
- Issue date Apr 3, 2012
- Cadence Design Systems, Inc.
- Hongliang Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing timing analysis and optimization...
- Patent number 7,930,675
- Issue date Apr 19, 2011
- Cadence Design Systems, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method of generating hierarchical block-level timing con...
- Patent number 7,926,011
- Issue date Apr 12, 2011
- Cadence Design Systems, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified timing analysis for model interface layout parasitics
- Patent number 6,704,697
- Issue date Mar 9, 2004
- Synopsys, Inc.
- Paul Berevoescu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Black box transparency in a circuit timing model
- Patent number 6,378,113
- Issue date Apr 23, 2002
- Synopsys, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING FULL...
- Publication number 20120254818
- Publication date Oct 4, 2012
- Cadence Design Systems, Inc.
- Dongzi Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPLEMENTING TIMING ANALYSIS AND OPTIMIZATION...
- Publication number 20090172619
- Publication date Jul 2, 2009
- Cadence Design Systems, Inc.
- Oleg Levitsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZATION OF TIMING MODELS USING BUS COMPRESSION
- Publication number 20040111247
- Publication date Jun 10, 2004
- Synopsys, Inc.
- Paul Berevoescu
- G06 - COMPUTING CALCULATING COUNTING

Oleg Levitsky

Person

Patents Grantslast 30 patents

Method, system, and computer program product for implementing proto...

Machine readable products for single pass parallel hierarchical tim...

Multi-phase models for timing closure of integrated circuit designs

Methods, systems, and articles of manufacture for implementing full...

Methods, systems, and articles of manufacture for synchronous hiera...

Timing budgeting of nested partitions for hierarchical integrated c...

Circuit design system and method of generating hierarchical block-l...

Methods for single pass parallel hierarchical timing closure of int...

Methods, systems, and articles of manufacture for synchronous hiera...

Methods for generating a user interface for timing budget analysis...

Method and system for implementing clock tree prototyping

Multi-phase models for timing closure of integrated circuit designs

Common path pessimism removal for hierarchical timing analysis

Systems for single pass parallel hierarchical timing closure of int...

User interface for timing budget analysis of integrated circuit des...

Flow methodology for single pass parallel hierarchical timing closu...

System and method of computing pin criticalities under process vari...

Method and system for implementing timing analysis and optimization...

System and method of generating hierarchical block-level timing con...

Unified timing analysis for model interface layout parasitics

Black box transparency in a circuit timing model

Patents Applicationslast 30 patents

METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING FULL...

METHOD AND SYSTEM FOR IMPLEMENTING TIMING ANALYSIS AND OPTIMIZATION...

OPTIMIZATION OF TIMING MODELS USING BUS COMPRESSION