Olivier Burg

Person

Lausanne, CH

People

Patents Grantslast 30 patents

Information Patent Grant
Multiplying delay-locked loop using sampling time-to-digital converter
- Patent number 10,250,264
- Issue date Apr 2, 2019
- Marvell World Trade Ltd.
- Haisong Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
All-digital phase locked loop (ADPLL) including a digital-to-time c...
- Patent number 9,740,175
- Issue date Aug 22, 2017
- Marvell World Trade Ltd.
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for avoiding dead zone effects in digital phas...
- Patent number 9,391,624
- Issue date Jul 12, 2016
- Marvell International Ltd.
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and devices for implementing all-digital phase locked loop
- Patent number 9,306,586
- Issue date Apr 5, 2016
- Marvell World Trade Ltd.
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and devices for implementing all-digital phase locked loop
- Patent number 9,036,763
- Issue date May 19, 2015
- Marvell World Trade Ltd., St. Michael
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and devices for multiple-mode radio frequency synthesizers
- Patent number 8,957,713
- Issue date Feb 17, 2015
- Marvell World Trade Ltd.
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and devices for multiple-mode radio frequency synthesizers
- Patent number 8,710,884
- Issue date Apr 29, 2014
- Marvell World Trade Ltd.
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLYING DELAY-LOCKED LOOP USING SAMPLING TIME-TO-DIGITAL CONVERTER
- Publication number 20170366191
- Publication date Dec 21, 2017
- Marvell World Trade Ltd.
- Haisong Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ANALOG FRACTIONAL-N PHASE-LOCKED LOOP
- Publication number 20170366376
- Publication date Dec 21, 2017
- Marvell World Trade Ltd.
- Haisong Wang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) INCLUDING A DIGITAL-TO-TIME C...
- Publication number 20170205772
- Publication date Jul 20, 2017
- Marvell World Trade Ltd.
- Olivier BURG
- G04 - HOROLOGY
Information Patent Application
METHODS AND DEVICES FOR IMPLEMENTING ALL-DIGITAL PHASE LOCKED LOOP
- Publication number 20150249455
- Publication date Sep 3, 2015
- Marvell World Trade Ltd.
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND DEVICES FOR MULTIPLE-MODE RADIO FREQUENCY SYNTHESIZERS
- Publication number 20140218086
- Publication date Aug 7, 2014
- Marvell World Trade Ltd.
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and Devices for Implementing All-Digital Phase Locked Loop
- Publication number 20120328065
- Publication date Dec 27, 2012
- Olivier Burg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and Devices for Multiple-Mode Radio Frequency Synthesizers
- Publication number 20120218014
- Publication date Aug 30, 2012
- Olivier BURG
- H03 - BASIC ELECTRONIC CIRCUITRY

Olivier Burg

Person

Patents Grantslast 30 patents

Multiplying delay-locked loop using sampling time-to-digital converter

All-digital phase locked loop (ADPLL) including a digital-to-time c...

Method and apparatus for avoiding dead zone effects in digital phas...

Methods and devices for implementing all-digital phase locked loop

Methods and devices for implementing all-digital phase locked loop

Methods and devices for multiple-mode radio frequency synthesizers

Methods and devices for multiple-mode radio frequency synthesizers

Patents Applicationslast 30 patents

MULTIPLYING DELAY-LOCKED LOOP USING SAMPLING TIME-TO-DIGITAL CONVERTER

ANALOG FRACTIONAL-N PHASE-LOCKED LOOP

ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) INCLUDING A DIGITAL-TO-TIME C...

METHODS AND DEVICES FOR IMPLEMENTING ALL-DIGITAL PHASE LOCKED LOOP

METHODS AND DEVICES FOR MULTIPLE-MODE RADIO FREQUENCY SYNTHESIZERS

Methods and Devices for Implementing All-Digital Phase Locked Loop

Methods and Devices for Multiple-Mode Radio Frequency Synthesizers