OREN BEN-KIKI

Person

Tel-Aviv, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for a hybrid latency-throughput processor
- Patent number 10,664,284
- Issue date May 26, 2020
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic to provide atomic range modification operations
- Patent number 10,528,345
- Issue date Jan 7, 2020
- Intel Corporation
- Ilan Pardo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for invocation of a multi threaded accelerator
- Patent number 10,346,195
- Issue date Jul 9, 2019
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a hybrid latency-throughput processor
- Patent number 10,255,077
- Issue date Apr 9, 2019
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for detecting numeric accumulation error
- Patent number 10,146,533
- Issue date Dec 4, 2018
- Intel Corporation
- Ilan Pardo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing core having shared front end unit
- Patent number 10,140,129
- Issue date Nov 27, 2018
- Intel Corporation
- Ilan Pardo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory address collision detection of ordered parallel threads with...
- Patent number 10,101,999
- Issue date Oct 16, 2018
- Intel Corporation
- Enrique De Lucas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for low-latency invocation of accelerators
- Patent number 10,095,521
- Issue date Oct 9, 2018
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for retrieving elements from a linked structure
- Patent number 10,095,517
- Issue date Oct 9, 2018
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for low-latency invocation of accelerators
- Patent number 10,089,113
- Issue date Oct 2, 2018
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for low-latency invocation of accelerators
- Patent number 10,083,037
- Issue date Sep 25, 2018
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for enforcement of reserved bits
- Patent number 9,934,090
- Issue date Apr 3, 2018
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User-level fork and join processors, methods, systems, and instruct...
- Patent number 9,747,108
- Issue date Aug 29, 2017
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory address collision detection of ordered parallel threads with...
- Patent number 9,542,193
- Issue date Jan 10, 2017
- Intel Corporation
- Enrique De Lucas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a hybrid latency-throughput processor
- Patent number 9,417,873
- Issue date Aug 16, 2016
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for low-latency invocation of accelerators
- Patent number 9,361,116
- Issue date Jun 7, 2016
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for memory-mapped register caching
- Patent number 9,189,398
- Issue date Nov 17, 2015
- Intel Corporation
- Ilan Pardo
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Apparatus and method for fast failure handling of instructions
- Patent number 9,053,025
- Issue date Jun 9, 2015
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR
- Publication number 20190196838
- Publication date Jun 27, 2019
- Intel Corporation
- OREN BEN-KIKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING CORE HAVING SHARED FRONT END UNIT
- Publication number 20190171462
- Publication date Jun 6, 2019
- Intel Corporation
- ILAN PARDO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Detecting Numeric Accumulation Error
- Publication number 20180088941
- Publication date Mar 29, 2018
- Intel Corporation
- ILAN PARDO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ENFORCEMENT OF RESERVED BITS
- Publication number 20170177439
- Publication date Jun 22, 2017
- Intel Corporation
- OREN BEN-KIKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR RETRIEVING ELEMENTS FROM A LINKED STRUCTURE
- Publication number 20170177341
- Publication date Jun 22, 2017
- Intel Corporation
- OREN BEN-KIKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ADDRESS COLLISION DETECTION OF ORDERED PARALLEL THREADS WITH...
- Publication number 20170147344
- Publication date May 25, 2017
- Intel Corporation
- ENRIQUE DE LUCAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
- Publication number 20170017491
- Publication date Jan 19, 2017
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
- Publication number 20170017492
- Publication date Jan 19, 2017
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND LOGIC TO PROVIDE ATOMIC RANGE OPERATIONS
- Publication number 20160283237
- Publication date Sep 29, 2016
- Ilan Pardo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USER-LEVEL FORK AND JOIN PROCESSORS, METHODS, SYSTEMS, AND INSTRUCT...
- Publication number 20160283245
- Publication date Sep 29, 2016
- Intel Corporation
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
- Publication number 20160246597
- Publication date Aug 25, 2016
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS
- Publication number 20140189332
- Publication date Jul 3, 2014
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR MEMORY-MAPPED REGISTER CACHING
- Publication number 20140189191
- Publication date Jul 3, 2014
- Ilan Pardo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR FAST FAILURE HANDLING OF INSTRUCTIONS
- Publication number 20140189426
- Publication date Jul 3, 2014
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR INVOCATION OF A MULTI THREADED ACCELERATOR
- Publication number 20140189713
- Publication date Jul 3, 2014
- Oren BEN-KIKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing Core Having Shared Front End Unit
- Publication number 20140189300
- Publication date Jul 3, 2014
- Name ILAN PARDO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR
- Publication number 20140189317
- Publication date Jul 3, 2014
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR TASK-SWITCHABLE SYNCHRONOUS HARDWARE ACCEL...
- Publication number 20140189333
- Publication date Jul 3, 2014
- Oren Ben-Kiki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Address Collision Detection Of Ordered Parallel Threads With...
- Publication number 20140189712
- Publication date Jul 3, 2014
- Enrique DE LUCAS
- G06 - COMPUTING CALCULATING COUNTING

OREN BEN-KIKI

Person

Patents Grantslast 30 patents

Apparatus and method for a hybrid latency-throughput processor

Instructions and logic to provide atomic range modification operations

Apparatus and method for invocation of a multi threaded accelerator

Apparatus and method for a hybrid latency-throughput processor

Instruction and logic for detecting numeric accumulation error

Processing core having shared front end unit

Memory address collision detection of ordered parallel threads with...

Apparatus and method for low-latency invocation of accelerators

Apparatus and method for retrieving elements from a linked structure

Apparatus and method for low-latency invocation of accelerators

Apparatus and method for low-latency invocation of accelerators

Apparatus and method for enforcement of reserved bits

User-level fork and join processors, methods, systems, and instruct...

Memory address collision detection of ordered parallel threads with...

Apparatus and method for a hybrid latency-throughput processor

Apparatus and method for low-latency invocation of accelerators

Apparatus and method for memory-mapped register caching

Apparatus and method for fast failure handling of instructions

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR

PROCESSING CORE HAVING SHARED FRONT END UNIT

Instruction and Logic for Detecting Numeric Accumulation Error

APPARATUS AND METHOD FOR ENFORCEMENT OF RESERVED BITS

APPARATUS AND METHOD FOR RETRIEVING ELEMENTS FROM A LINKED STRUCTURE

MEMORY ADDRESS COLLISION DETECTION OF ORDERED PARALLEL THREADS WITH...

APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS

APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS

INSTRUCTIONS AND LOGIC TO PROVIDE ATOMIC RANGE OPERATIONS

USER-LEVEL FORK AND JOIN PROCESSORS, METHODS, SYSTEMS, AND INSTRUCT...

APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS

APPARATUS AND METHOD FOR LOW-LATENCY INVOCATION OF ACCELERATORS

APPARATUS AND METHOD FOR MEMORY-MAPPED REGISTER CACHING

APPARATUS AND METHOD FOR FAST FAILURE HANDLING OF INSTRUCTIONS

APPARATUS AND METHOD FOR INVOCATION OF A MULTI THREADED ACCELERATOR

Processing Core Having Shared Front End Unit

APPARATUS AND METHOD FOR A HYBRID LATENCY-THROUGHPUT PROCESSOR

APPARATUS AND METHOD FOR TASK-SWITCHABLE SYNCHRONOUS HARDWARE ACCEL...

Memory Address Collision Detection Of Ordered Parallel Threads With...