Osamu S. Nakagawa

Person

Redwood City, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Optimization of integrated circuits for a reticle transmission proc...
- Patent number 9,218,446
- Issue date Dec 22, 2015
- GLOBALFOUNDRIES Inc.
- Pavan Bashaboina
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell array and density features with decoupling capacitors
- Patent number 8,716,869
- Issue date May 6, 2014
- GLOBALFOUNDRIES Inc.
- Osamu S. Nakagawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Designing layout for internet datacenter cooling
- Patent number 7,313,503
- Issue date Dec 25, 2007
- Hewlett-Packard Development Company, L.P.
- Osamu Samuel Nakagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to reduce leakage power in an electronic device
- Patent number 6,981,231
- Issue date Dec 27, 2005
- Hewlett-Packard Development Company, L.P.
- Weize Xie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for determining a plurality of clock delay values...
- Patent number 6,925,555
- Issue date Aug 2, 2005
- Hewlett-Packard Development Company, L.P.
- Norman Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reducing current surge using multi-stage ramp shunting
- Patent number 6,661,281
- Issue date Dec 9, 2003
- Hewlett-Packard Development Company, L.P.
- Osamu Samuel Nakagawa
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Partial swing low power CMOS logic circuits
- Patent number 6,621,305
- Issue date Sep 16, 2003
- Hewlett-Packard Development Company, L.P.
- Osamu Samuel Nakagawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System for improving circuit simulations by utilizing a simplified...
- Patent number 6,567,960
- Issue date May 20, 2003
- Hewlett-Packard Development L.P.
- Norman Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel push algorithm detecting constraints to minimize clock skew
- Patent number 6,566,924
- Issue date May 20, 2003
- Hewlett-Packard Development Company L.P.
- Shen Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ramp loading circuit for reducing current surges
- Patent number 6,462,607
- Issue date Oct 8, 2002
- Hewlett-Packard Company
- Osamu Samuel Nakagawa
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CHIP STRUCTURE WITH STEGANOGRAPHIC FILL SHAPE PATTERN
- Publication number 20240232484
- Publication date Jul 11, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Osamu S. Nakagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER-SCALE CHIP STRUCTURE AND METHOD AND SYSTEM FOR DESIGNING THE...
- Publication number 20240105633
- Publication date Mar 28, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Osamu Samuel Nakagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZATION OF INTEGRATED CIRCUITS FOR A RETICLE TRANSMISSION PROC...
- Publication number 20150363532
- Publication date Dec 17, 2015
- GLOBALFOUNDRIES INC.
- Pavan Bashaboina
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cell Array with Density Features
- Publication number 20130193554
- Publication date Aug 1, 2013
- GLOBALFOUNDRIES INC.
- Osamu S. Nakagawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for high-dielectric constant metal-insulator metal capacito...
- Publication number 20040082175
- Publication date Apr 29, 2004
- Osamu Samuel Nakagawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method to reduce leakage power in an electronic device
- Publication number 20030163792
- Publication date Aug 28, 2003
- Weize Xie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Designing layout for internet datacenter cooling
- Publication number 20030158718
- Publication date Aug 21, 2003
- Osamu Samuel Nakagawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for reducing current surge using multi-stage ramp shunting
- Publication number 20030098742
- Publication date May 29, 2003
- Osamu Samuel Nakagawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for predictive power ramping
- Publication number 20030084353
- Publication date May 1, 2003
- Norman Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for improving circuit simulations by utilizing a simplified...
- Publication number 20030070148
- Publication date Apr 10, 2003
- Norman Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Partial swing low power CMOS logic circuits
- Publication number 20030030467
- Publication date Feb 13, 2003
- Osamu Samuel Nakagawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Optimization of clock scheduling for a synchronous system
- Publication number 20030023327
- Publication date Jan 30, 2003
- Norman Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel push algorithm detecting constraints to minimize clock skew
- Publication number 20030020527
- Publication date Jan 30, 2003
- Shen Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High-dielectric constant metal-insulator metal capacitor in VLSI mu...
- Publication number 20030001188
- Publication date Jan 2, 2003
- Osamu Samuel Nakagawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for high-dielectric constant metal-insulator metal capacito...
- Publication number 20030003665
- Publication date Jan 2, 2003
- Osamu Samuel Nakagawa
- H01 - BASIC ELECTRIC ELEMENTS

Osamu S. Nakagawa

Person

Patents Grantslast 30 patents

Optimization of integrated circuits for a reticle transmission proc...

Cell array and density features with decoupling capacitors

Designing layout for internet datacenter cooling

System and method to reduce leakage power in an electronic device

System and method for determining a plurality of clock delay values...

Method for reducing current surge using multi-stage ramp shunting

Partial swing low power CMOS logic circuits

System for improving circuit simulations by utilizing a simplified...

Parallel push algorithm detecting constraints to minimize clock skew

Ramp loading circuit for reducing current surges

Patents Applicationslast 30 patents

CHIP STRUCTURE WITH STEGANOGRAPHIC FILL SHAPE PATTERN

WAFER-SCALE CHIP STRUCTURE AND METHOD AND SYSTEM FOR DESIGNING THE...

OPTIMIZATION OF INTEGRATED CIRCUITS FOR A RETICLE TRANSMISSION PROC...

Cell Array with Density Features

Process for high-dielectric constant metal-insulator metal capacito...

System and method to reduce leakage power in an electronic device

Designing layout for internet datacenter cooling

Method for reducing current surge using multi-stage ramp shunting

System and method for predictive power ramping

System for improving circuit simulations by utilizing a simplified...

Partial swing low power CMOS logic circuits

Optimization of clock scheduling for a synchronous system

Parallel push algorithm detecting constraints to minimize clock skew

High-dielectric constant metal-insulator metal capacitor in VLSI mu...

Process for high-dielectric constant metal-insulator metal capacito...