Otto A. Torreiter

Person

Boeblingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Logic built-in self-test of an electronic circuit
- Patent number 11,574,695
- Issue date Feb 7, 2023
- International Business Machines Corporation
- Alejandro Alberto Cook Lobo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device for positioning a semiconductor die in a wafer prober
- Patent number 11,262,381
- Issue date Mar 1, 2022
- International Business Machines Corporation
- Otto Andreas Torreiter
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with optical tunnel
- Patent number 11,239,152
- Issue date Feb 1, 2022
- International Business Machines Corporation
- Otto Andreas Torreiter
- G01 - MEASURING TESTING
Information Patent Grant
Stressing integrated circuits using a radiation source
- Patent number 11,209,479
- Issue date Dec 28, 2021
- International Business Machines Corporation
- Martin Eckert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
On-chip hardware-controlled window strobing
- Patent number 10,288,684
- Issue date May 14, 2019
- International Business Machines Corporation
- Thomas Gentner
- G01 - MEASURING TESTING
Information Patent Grant
On-chip hardware-controlled window strobing
- Patent number 10,281,527
- Issue date May 7, 2019
- International Business Machines Corporation
- Thomas Gentner
- G01 - MEASURING TESTING
Information Patent Grant
Method for electrical testing of a 3-D chip stack
- Patent number 10,114,069
- Issue date Oct 30, 2018
- International Business Machines Corporation
- Martin Eckert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Layout effect characterization for integrated circuits
- Patent number 10,114,914
- Issue date Oct 30, 2018
- International Business Machines Corporation
- Martin Eckert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip attach frame
- Patent number 10,056,346
- Issue date Aug 21, 2018
- International Business Machines Corporation
- Martin Eckert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer probe alignment
- Patent number 9,977,053
- Issue date May 22, 2018
- International Business Machines Corporation
- Joerg G. Appinger
- G01 - MEASURING TESTING
Information Patent Grant
Wafer probe alignment
- Patent number 9,927,463
- Issue date Mar 27, 2018
- International Business Machines Corporation
- Joerg G. Appinger
- G01 - MEASURING TESTING
Information Patent Grant
Layout effect characterization for integrated circuits
- Patent number 9,904,748
- Issue date Feb 27, 2018
- International Business Machines Corporation
- Martin Eckert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout effect characterization for integrated circuits
- Patent number 9,740,813
- Issue date Aug 22, 2017
- International Business Machines Corporation
- Martin Eckert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measuring power consumption in an integrated circuit
- Patent number 9,709,625
- Issue date Jul 18, 2017
- International Business Machines Corporation
- Martin Eckert
- G01 - MEASURING TESTING
Information Patent Grant
Chip attach frame
- Patent number 9,686,895
- Issue date Jun 20, 2017
- International Business Machines Corporation
- Martin Eckert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for performing built-in self-tests
- Patent number 9,679,665
- Issue date Jun 13, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Grant
RAM at speed flexible timing and setup control
- Patent number 9,627,090
- Issue date Apr 18, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Grant
RAM at speed flexible timing and setup control
- Patent number 9,627,017
- Issue date Apr 18, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Grant
Determining categories for memory fail conditions
- Patent number 9,620,244
- Issue date Apr 11, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Grant
Soldering three dimensional integrated circuits
- Patent number 9,496,188
- Issue date Nov 15, 2016
- International Business Machines Corporation
- Martin Eckert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Determining categories for memory fail conditions
- Patent number 9,401,222
- Issue date Jul 26, 2016
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Grant
Ball grid array configuration for reliable testing
- Patent number 9,322,848
- Issue date Apr 26, 2016
- GLOBALFOUNDRIES Inc.
- Otto A. Torreiter
- G01 - MEASURING TESTING
Information Patent Grant
System for electrical testing and manufacturing of a 3-D chip stack...
- Patent number 9,250,289
- Issue date Feb 2, 2016
- International Business Machines Corporation
- Martin Eckert
- G01 - MEASURING TESTING
Information Patent Grant
Ball grid array configuration for reliable testing
- Patent number 9,217,758
- Issue date Dec 22, 2015
- GLOBALFOUNDRIES Inc.
- Otto A. Torreiter
- G01 - MEASURING TESTING
Information Patent Grant
Network power fault detection
- Patent number 9,094,306
- Issue date Jul 28, 2015
- International Business Machines Corporation
- Martin Eckert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Determining local voltage in an electronic system
- Patent number 8,866,504
- Issue date Oct 21, 2014
- International Business Machines Corporation
- Martin Eckert
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for performing self-tests in an electronic system
- Patent number 8,659,310
- Issue date Feb 25, 2014
- International Business Machines Corporation
- Martin Eckert
- G01 - MEASURING TESTING
Information Patent Grant
Chip attach frame
- Patent number 8,535,956
- Issue date Sep 17, 2013
- International Business Machines Corporation
- Martin Eckert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and system for testing bit failures in array elements of an...
- Patent number 8,010,934
- Issue date Aug 30, 2011
- International Business Machines Corporation
- Joachim Kneisel
- G01 - MEASURING TESTING
Information Patent Grant
Wordline booster design structure and method of operating a wordine...
- Patent number 7,921,388
- Issue date Apr 5, 2011
- International Business Machines Corporation
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LOGIC BUILT-IN SELF-TEST OF AN ELECTRONIC CIRCUIT
- Publication number 20230035157
- Publication date Feb 2, 2023
- International Business Machines Corporation
- Alejandro Alberto Cook Lobo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE FOR POSITIONING A SEMICONDUCTOR DIE IN A WAFER PROBER
- Publication number 20210215738
- Publication date Jul 15, 2021
- International Business Machines Corporation
- Otto Andreas Torreiter
- G01 - MEASURING TESTING
Information Patent Application
STRESSING INTEGRATED CIRCUITS USING A RADIATION SOURCE
- Publication number 20210123969
- Publication date Apr 29, 2021
- International Business Machines Corporation
- Martin Eckert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT WITH OPTICAL TUNNEL
- Publication number 20210066183
- Publication date Mar 4, 2021
- International Business Machines Corporation
- Otto Andreas Torreiter
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP HARDWARE-CONTROLLED WINDOW STROBING
- Publication number 20180364309
- Publication date Dec 20, 2018
- International Business Machines Corporation
- Thomas Gentner
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP HARDWARE-CONTROLLED WINDOW STROBING
- Publication number 20180364308
- Publication date Dec 20, 2018
- International Business Machines Corporation
- Thomas Gentner
- G01 - MEASURING TESTING
Information Patent Application
LAYOUT EFFECT CHARACTERIZATION FOR INTEGRATED CIRCUITS
- Publication number 20180107771
- Publication date Apr 19, 2018
- International Business Machines Corporation
- Martin Eckert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP ATTACH FRAME
- Publication number 20170162534
- Publication date Jun 8, 2017
- International Business Machines Corporation
- Martin Eckert
- G01 - MEASURING TESTING
Information Patent Application
WAFER PROBE ALIGNMENT
- Publication number 20170108547
- Publication date Apr 20, 2017
- International Business Machines Corporation
- Joerg G. APPINGER
- G01 - MEASURING TESTING
Information Patent Application
WAFER PROBE ALIGNMENT
- Publication number 20170108534
- Publication date Apr 20, 2017
- International Business Machines Corporation
- Joerg G. APPINGER
- G01 - MEASURING TESTING
Information Patent Application
RAM AT SPEED FLEXIBLE TIMING AND SETUP CONTROL
- Publication number 20170092341
- Publication date Mar 30, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Application
RAM AT SPEED FLEXIBLE TIMING AND SETUP CONTROL
- Publication number 20170092377
- Publication date Mar 30, 2017
- International Business Machines Corporation
- Martin Eckert
- G11 - INFORMATION STORAGE
Information Patent Application
SOLDERING THREE DIMENSIONAL INTEGRATED CIRCUITS
- Publication number 20160293497
- Publication date Oct 6, 2016
- International Business Machines Corporation
- Martin Eckert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM FOR ELECTRICAL TESTING AND MANUFACTURING OF A 3-D CHIP STACK...
- Publication number 20160097807
- Publication date Apr 7, 2016
- International Business Machines Corporation
- Martin ECKERT
- G01 - MEASURING TESTING
Information Patent Application
CHIP ATTACH FRAME
- Publication number 20150201537
- Publication date Jul 16, 2015
- International Business Machines Corporation
- Martin Eckert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CHIP ATTACH FRAME
- Publication number 20150059166
- Publication date Mar 5, 2015
- International Business Machines Corporation
- Martin Eckert
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
BALL GRID ARRAY CONFIGURATION FOR RELIABLE TESTING
- Publication number 20150008949
- Publication date Jan 8, 2015
- International Business Machines Corporation
- Otto A. Torreiter
- G01 - MEASURING TESTING
Information Patent Application
BALL GRID ARRAY CONFIGURATION FOR RELIABLE TESTING
- Publication number 20150008947
- Publication date Jan 8, 2015
- International Business Machines Corporation
- Otto A. Torreiter
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR ELECTRICAL TESTING AND MANUFACTURING OF A 3-D CHIP STACK...
- Publication number 20140300382
- Publication date Oct 9, 2014
- International Business Machines Corporation
- Martin ECKERT
- G01 - MEASURING TESTING
Information Patent Application
NETWORK POWER FAULT DETECTION
- Publication number 20130343200
- Publication date Dec 26, 2013
- Martin Eckert
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CHIP ATTACH FRAME
- Publication number 20130207250
- Publication date Aug 15, 2013
- International Business Machines Corporation
- Martin Eckert
- G01 - MEASURING TESTING
Information Patent Application
DETERMINING LOCAL VOLTAGE IN AN ELECTRONIC SYSTEM
- Publication number 20120146674
- Publication date Jun 14, 2012
- International Business Machines Corporation
- Martin Eckert
- G01 - MEASURING TESTING
Information Patent Application
MEASURING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT
- Publication number 20120130657
- Publication date May 24, 2012
- International Business Machines Corporation
- Martin ECKERT
- G01 - MEASURING TESTING
Information Patent Application
Method And System For Performing Self-Tests In An Electronic System
- Publication number 20120013356
- Publication date Jan 19, 2012
- International Business Machines Corporation
- Martin Eckert
- G01 - MEASURING TESTING
Information Patent Application
Method and System for Testing Bit Failures in Array Elements of an...
- Publication number 20080301596
- Publication date Dec 4, 2008
- Joachim Kneisel
- G01 - MEASURING TESTING
Information Patent Application
Wordline Booster Design Structure and Method of Operating a Wordlin...
- Publication number 20080068902
- Publication date Mar 20, 2008
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Application
Wordline Booster Circuit and Method of Operating a Wordline Booster...
- Publication number 20080068901
- Publication date Mar 20, 2008
- Sebastian Ehrenreich
- G11 - INFORMATION STORAGE
Information Patent Application
Method and an integrated circuit for performing a test
- Publication number 20070124637
- Publication date May 31, 2007
- Gottfried Goldrian
- G01 - MEASURING TESTING
Information Patent Application
Self-test for leakage current of driver/receiver stages
- Publication number 20020079915
- Publication date Jun 27, 2002
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING
Information Patent Application
Self-test with split, asymmetric controlled driver output stage
- Publication number 20020078400
- Publication date Jun 20, 2002
- International Business Machines Corporation
- Ulrich Baur
- G01 - MEASURING TESTING

Otto A. Torreiter

Person

Patents Grantslast 30 patents

Logic built-in self-test of an electronic circuit

Device for positioning a semiconductor die in a wafer prober

Integrated circuit with optical tunnel

Stressing integrated circuits using a radiation source

On-chip hardware-controlled window strobing

On-chip hardware-controlled window strobing

Method for electrical testing of a 3-D chip stack

Layout effect characterization for integrated circuits

Chip attach frame

Wafer probe alignment

Wafer probe alignment

Layout effect characterization for integrated circuits

Layout effect characterization for integrated circuits

Measuring power consumption in an integrated circuit

Chip attach frame

Method for performing built-in self-tests

RAM at speed flexible timing and setup control

RAM at speed flexible timing and setup control

Determining categories for memory fail conditions

Soldering three dimensional integrated circuits

Determining categories for memory fail conditions

Ball grid array configuration for reliable testing

System for electrical testing and manufacturing of a 3-D chip stack...

Ball grid array configuration for reliable testing

Network power fault detection

Determining local voltage in an electronic system

Method and system for performing self-tests in an electronic system

Chip attach frame

Method and system for testing bit failures in array elements of an...

Wordline booster design structure and method of operating a wordine...

Patents Applicationslast 30 patents

LOGIC BUILT-IN SELF-TEST OF AN ELECTRONIC CIRCUIT

DEVICE FOR POSITIONING A SEMICONDUCTOR DIE IN A WAFER PROBER

STRESSING INTEGRATED CIRCUITS USING A RADIATION SOURCE

INTEGRATED CIRCUIT WITH OPTICAL TUNNEL

ON-CHIP HARDWARE-CONTROLLED WINDOW STROBING

ON-CHIP HARDWARE-CONTROLLED WINDOW STROBING

LAYOUT EFFECT CHARACTERIZATION FOR INTEGRATED CIRCUITS

CHIP ATTACH FRAME

WAFER PROBE ALIGNMENT

WAFER PROBE ALIGNMENT

RAM AT SPEED FLEXIBLE TIMING AND SETUP CONTROL

RAM AT SPEED FLEXIBLE TIMING AND SETUP CONTROL

SOLDERING THREE DIMENSIONAL INTEGRATED CIRCUITS

SYSTEM FOR ELECTRICAL TESTING AND MANUFACTURING OF A 3-D CHIP STACK...

CHIP ATTACH FRAME

CHIP ATTACH FRAME

BALL GRID ARRAY CONFIGURATION FOR RELIABLE TESTING

BALL GRID ARRAY CONFIGURATION FOR RELIABLE TESTING

SYSTEM FOR ELECTRICAL TESTING AND MANUFACTURING OF A 3-D CHIP STACK...

NETWORK POWER FAULT DETECTION

CHIP ATTACH FRAME

DETERMINING LOCAL VOLTAGE IN AN ELECTRONIC SYSTEM

MEASURING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT

Method And System For Performing Self-Tests In An Electronic System

Method and System for Testing Bit Failures in Array Elements of an...

Wordline Booster Design Structure and Method of Operating a Wordlin...

Wordline Booster Circuit and Method of Operating a Wordline Booster...

Method and an integrated circuit for performing a test

Self-test for leakage current of driver/receiver stages

Self-test with split, asymmetric controlled driver output stage