Owen W. Jungroth

Person

Sonora, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatuses and methods for concurrently accessing multiple partiti...
- Patent number 11,768,603
- Issue date Sep 26, 2023
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resistance reduction for word lines in memory arrays
- Patent number 11,587,874
- Issue date Feb 21, 2023
- Intel Corporation
- Sung-Taeg Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple partiti...
- Patent number 11,354,040
- Issue date Jun 7, 2022
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory arrays with bonded and shared logic circuitry
- Patent number 10,923,450
- Issue date Feb 16, 2021
- Intel Corporation
- Richard Fastow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatuses and methods for concurrently accessing multiple partiti...
- Patent number 10,719,237
- Issue date Jul 21, 2020
- Micron Technology, Inc.
- Rajesh Sundaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three-dimensional (3D) memory with shared control circuitry using w...
- Patent number 10,651,153
- Issue date May 12, 2020
- Intel Corporation
- Richard Fastow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wordline bridge in a 3D memory array
- Patent number 10,515,973
- Issue date Dec 24, 2019
- Intel Corporation
- Deepak Thimmegowda
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing stress across capacitors used in...
- Patent number RE41217
- Issue date Apr 13, 2010
- Intel Corporation
- Ramkarthik Ganesan
- 363 - Electric power conversion systems
Information Patent Grant
Method and apparatus for matched-reference sensing architecture for...
- Patent number 6,831,862
- Issue date Dec 14, 2004
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for matched-reference sensing architecture for...
- Patent number 6,515,906
- Issue date Feb 4, 2003
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage driver for a memory
- Patent number 6,449,211
- Issue date Sep 10, 2002
- Intel Corporation
- Owen W. Jungroth
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory and method for transferring data using a...
- Patent number 6,418,506
- Issue date Jul 9, 2002
- Intel Corporation
- Richard D. Pashley
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing stress across capacitors used in...
- Patent number 6,297,974
- Issue date Oct 2, 2001
- Intel Corporation
- Ramkarthik Ganesan
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
System and method for allocating and sharingpage buffers for a flas...
- Patent number 5,802,552
- Issue date Sep 1, 1998
- Intel Corporation
- Mickey L. Fandrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile memory blocking architecture and redundancy
- Patent number 5,621,690
- Issue date Apr 15, 1997
- Intel Corporation
- Owen W. Jungroth
- G11 - INFORMATION STORAGE
Information Patent Grant
Architecture for reading information from a memory array
- Patent number 5,430,677
- Issue date Jul 4, 1995
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Override timing control circuitry and method for terminating progra...
- Patent number 5,414,829
- Issue date May 9, 1995
- Intel Corporation
- Mickey L. Fandrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference switching circuit for flash EPROM
- Patent number 5,390,146
- Issue date Feb 14, 1995
- Intel Corporation
- Gregory E. Atwood
- G11 - INFORMATION STORAGE
Information Patent Grant
Single cell reference scheme for flash memory sensing and program s...
- Patent number 5,386,388
- Issue date Jan 31, 1995
- Intel Corporation
- Gregory E. Atwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile memory with automatic power supply configuration
- Patent number 5,363,335
- Issue date Nov 8, 1994
- Intel Corporation
- Owen Jungroth
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuitry and method for discharging a drain of a cell of a non-vol...
- Patent number 5,265,059
- Issue date Nov 23, 1993
- Intel Corporation
- Steven E. Wells
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory blocking architecture
- Patent number 5,249,158
- Issue date Sep 28, 1993
- Intel Corporation
- Virgil N. Kynett
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for preventing the erasure and programming of...
- Patent number 4,975,883
- Issue date Dec 4, 1990
- Intel Corporation
- Alan E. Baker
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage margining circuit for flash eprom
- Patent number 4,875,188
- Issue date Oct 17, 1989
- Intel Corporation
- Owen W. Jungroth
- G11 - INFORMATION STORAGE
Information Patent Grant
A circuit for providing a load for the charging of an EPROM cell
- Patent number 4,858,186
- Issue date Aug 15, 1989
- Intle Corporation
- Owen W. Jungroth
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS...
- Publication number 20220359441
- Publication date Nov 10, 2022
- Intel Corporation
- Khaled HASNAT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...
- Publication number 20220261151
- Publication date Aug 18, 2022
- Micron Technology, Inc.
- RAJESH SUNDARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESISTANCE REDUCTION FOR WORD LINES IN MEMORY ARRAYS
- Publication number 20210265278
- Publication date Aug 26, 2021
- Intel Corporation
- Sung-Taeg Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ARRAYS WITH BONDED AND SHARED LOGIC CIRCUITRY
- Publication number 20200395328
- Publication date Dec 17, 2020
- Intel Corporation
- Richard Fastow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...
- Publication number 20200341635
- Publication date Oct 29, 2020
- Micron Technology, Inc.
- RAJESH SUNDARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH A SPLIT STAIRCASE
- Publication number 20200152650
- Publication date May 14, 2020
- Intel Corporation
- Deepak Thimmegowda
- G11 - INFORMATION STORAGE
Information Patent Application
WORDLINE BRIDGE IN A 3D MEMORY ARRAY
- Publication number 20190043874
- Publication date Feb 7, 2019
- Intel Corporation
- Deepak Thimmegowda
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL (3D) MEMORY WITH SHARED CONTROL CIRCUITRY USING W...
- Publication number 20190043836
- Publication date Feb 7, 2019
- Intel Corporation
- Richard FASTOW
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...
- Publication number 20170199666
- Publication date Jul 13, 2017
- Micron Technology, Inc.
- RAJESH SUNDARAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for matched-reference sensing architecture for...
- Publication number 20030090949
- Publication date May 15, 2003
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for matched-reference sensing architecture for...
- Publication number 20020085423
- Publication date Jul 4, 2002
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE

Owen W. Jungroth

Person

Patents Grantslast 30 patents

Apparatuses and methods for concurrently accessing multiple partiti...

Resistance reduction for word lines in memory arrays

Apparatuses and methods for concurrently accessing multiple partiti...

Memory arrays with bonded and shared logic circuitry

Apparatuses and methods for concurrently accessing multiple partiti...

Three-dimensional (3D) memory with shared control circuitry using w...

Wordline bridge in a 3D memory array

Method and apparatus for reducing stress across capacitors used in...

Method and apparatus for matched-reference sensing architecture for...

Method and apparatus for matched-reference sensing architecture for...

Voltage driver for a memory

Integrated circuit memory and method for transferring data using a...

Method and apparatus for reducing stress across capacitors used in...

System and method for allocating and sharingpage buffers for a flas...

Nonvolatile memory blocking architecture and redundancy

Architecture for reading information from a memory array

Override timing control circuitry and method for terminating progra...

Reference switching circuit for flash EPROM

Single cell reference scheme for flash memory sensing and program s...

Nonvolatile memory with automatic power supply configuration

Circuitry and method for discharging a drain of a cell of a non-vol...

Flash memory blocking architecture

Method and apparatus for preventing the erasure and programming of...

Voltage margining circuit for flash eprom

A circuit for providing a load for the charging of an EPROM cell

Patents Applicationslast 30 patents

THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS...

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...

RESISTANCE REDUCTION FOR WORD LINES IN MEMORY ARRAYS

MEMORY ARRAYS WITH BONDED AND SHARED LOGIC CIRCUITRY

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...

MEMORY DEVICE WITH A SPLIT STAIRCASE

WORDLINE BRIDGE IN A 3D MEMORY ARRAY

THREE-DIMENSIONAL (3D) MEMORY WITH SHARED CONTROL CIRCUITRY USING W...

APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITI...

Method and apparatus for matched-reference sensing architecture for...

Method and apparatus for matched-reference sensing architecture for...