PADMANABHA I. VENKITAKRISHNAN

Person

SUNNYVALE, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for deriving the benchmark program for estimating the maximu...
- Patent number 7,003,441
- Issue date Feb 21, 2006
- Hewlett-Packard Development Company, L.P.
- Padmanabha Venkitakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streamlined cache coherency protocol system and method for a multip...
- Patent number 6,918,012
- Issue date Jul 12, 2005
- Hewlett-Packard Development Company, L.P.
- Padmanabha I. Venkitakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip multiprocessor with multiple operating systems
- Patent number 6,874,014
- Issue date Mar 29, 2005
- Hewlett-Packard Development Company, L.P.
- Stephen E. Richardson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable, re-configurable crossbar switch architecture for multi-pr...
- Patent number 6,597,692
- Issue date Jul 22, 2003
- Hewlett-Packard Development, L.P.
- Padmanabha I. Venkitakrishnan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for estimating the power consumed in a microprocessor
- Patent number 6,513,145
- Issue date Jan 28, 2003
- Hewlett-Packard Company
- Padmanabha Venkitakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable system control unit for distributed shared memory multi-pr...
- Patent number 6,378,029
- Issue date Apr 23, 2002
- Hewlett-Packard Company
- Padmanabha I. Venkitakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed directory cache coherence multi-processor computer arch...
- Patent number 6,374,331
- Issue date Apr 16, 2002
- Hewlett-Packard Company
- Gopalakrishnan Janakiraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Backup redundant routing system crossbar switch architecture for mu...
- Patent number 6,263,415
- Issue date Jul 17, 2001
- Hewlett-Packard Co.
- Padmanabha I. Venkitakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-sliced, dual-bus design of integrated circuits
- Patent number 4,641,247
- Issue date Feb 3, 1987
- Advanced Micro Devices, Inc.
- Ronald C. Laugesen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Data retention system with a plurality of access protocols
- Publication number 20060190552
- Publication date Aug 24, 2006
- Richard H. Henze
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SCALABLE, RE-CONFIGURABLE CROSSBAR SWITCH ARCHITECTURE FOR MULTI-PR...
- Publication number 20030128709
- Publication date Jul 10, 2003
- PADMANABHA I. VENKITAKRISHNAN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Streamlined cache coherency protocol system and method for a multip...
- Publication number 20030046495
- Publication date Mar 6, 2003
- Padmanabha I. Venkitakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for deriving the benchmark program for estimating the maximu...
- Publication number 20030037270
- Publication date Feb 20, 2003
- Padmanabha Venkitakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache coherent split transaction memory bus architecture and protoc...
- Publication number 20030023794
- Publication date Jan 30, 2003
- Padmanabha I. Venkitakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip multiprocessor with multiple operating systems
- Publication number 20020184328
- Publication date Dec 5, 2002
- Stephen E. Richardson
- G06 - COMPUTING CALCULATING COUNTING

PADMANABHA I. VENKITAKRISHNAN

Person

Patents Grantslast 30 patents

Method for deriving the benchmark program for estimating the maximu...

Streamlined cache coherency protocol system and method for a multip...

Chip multiprocessor with multiple operating systems

Scalable, re-configurable crossbar switch architecture for multi-pr...

Method for estimating the power consumed in a microprocessor

Scalable system control unit for distributed shared memory multi-pr...

Distributed directory cache coherence multi-processor computer arch...

Backup redundant routing system crossbar switch architecture for mu...

Bit-sliced, dual-bus design of integrated circuits

Patents Applicationslast 30 patents

Data retention system with a plurality of access protocols

SCALABLE, RE-CONFIGURABLE CROSSBAR SWITCH ARCHITECTURE FOR MULTI-PR...

Streamlined cache coherency protocol system and method for a multip...

Method for deriving the benchmark program for estimating the maximu...

Cache coherent split transaction memory bus architecture and protoc...

Chip multiprocessor with multiple operating systems