Pak Leung

Person

People

Patents Grantslast 30 patents

Information Patent Grant
Multiple step anneal method and semiconductor formed by multiple st...
- Patent number 9,018,089
- Issue date Apr 28, 2015
- International Business Machines Corporation
- Eric G. Liniger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Generation of metal holes by via mutation
- Patent number 8,378,493
- Issue date Feb 19, 2013
- Infineon Technologies AG
- Robert C. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo hybrid structure for low K interconnect integration
- Patent number 7,955,968
- Issue date Jun 7, 2011
- FREESCALE SEMICONDUCTOR, INC.
- Pak K. Leung
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method of producing a semiconductor interconnect architecture inclu...
- Patent number 7,875,544
- Issue date Jan 25, 2011
- Infineon Technologies AG
- Robert C. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming interconnects with air gaps
- Patent number 7,790,601
- Issue date Sep 7, 2010
- International Business Machines Corporation
- Samuel S. S. Choi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having structural support for a flip-chip interc...
- Patent number 7,247,552
- Issue date Jul 24, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Generation of metal holes by via mutation
- Patent number 7,188,321
- Issue date Mar 6, 2007
- International Business Machines Corporation
- Robert C. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stress-relief layer for semiconductor applications
- Patent number 6,960,835
- Issue date Nov 1, 2005
- Infineon Technologies AG
- Hans-Joachim Barth
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MULTIPLE STEP ANNEAL METHOD AND SEMICONDUCTOR FORMED BY MULTIPLE ST...
- Publication number 20130049207
- Publication date Feb 28, 2013
- International Business Machines Corporation
- Eric G. Liniger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GENERATION OF METAL HOLES BY VIA MUTATION
- Publication number 20110079921
- Publication date Apr 7, 2011
- Robert C. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pseudo Hybrid Structure for Low K Interconnect Integration
- Publication number 20100227471
- Publication date Sep 9, 2010
- Pak K. Leung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Generation of metal holes by via mutation
- Publication number 20070118828
- Publication date May 24, 2007
- International Business Machines Corporation
- Robert C. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit having structural support for a flip-chip interc...
- Publication number 20060154470
- Publication date Jul 13, 2006
- Scott K. Pozder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Generation of metal holes by via mutation
- Publication number 20050098898
- Publication date May 12, 2005
- Robert C. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stress-relief layer for semiconductor applications
- Publication number 20050093159
- Publication date May 5, 2005
- Hans-Joachim Barth
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Multiple step anneal method and semiconductor formed by multiple st...

Generation of metal holes by via mutation

Pseudo hybrid structure for low K interconnect integration

Method of producing a semiconductor interconnect architecture inclu...

Forming interconnects with air gaps

Integrated circuit having structural support for a flip-chip interc...

Generation of metal holes by via mutation

Stress-relief layer for semiconductor applications

Patents Applicationslast 30 patents

MULTIPLE STEP ANNEAL METHOD AND SEMICONDUCTOR FORMED BY MULTIPLE ST...

GENERATION OF METAL HOLES BY VIA MUTATION

Pseudo Hybrid Structure for Low K Interconnect Integration

Generation of metal holes by via mutation

Integrated circuit having structural support for a flip-chip interc...

Generation of metal holes by via mutation

Stress-relief layer for semiconductor applications